C8051F303 Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

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C8051F303

Mixed Signal ISP Flash MCU Family

Unspecified 

C8051F300/1/2/3/4/5

Figure 11.2. 32.768 kHz External Crystal Example.................................................. 97

12. Port Input/Output

Figure 12.1. Port I/O Functional Block Diagram ....................................................... 99

Figure 12.2. Port I/O Cell Block Diagram ................................................................. 99

Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 100

Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 101

13. SMBus

Figure 13.1. SMBus Block Diagram ....................................................................... 107

Figure 13.2. Typical SMBus Configuration ............................................................. 108

Figure 13.3. SMBus Transaction ............................................................................ 109

Figure 13.4. Typical SMBus SCL Generation......................................................... 113

Figure 13.5. Typical Master Transmitter Sequence................................................ 119

Figure 13.6. Typical Master Receiver Sequence.................................................... 120

Figure 13.7. Typical Slave Receiver Sequence...................................................... 121

Figure 13.8. Typical Slave Transmitter Sequence.................................................. 122

14. UART0

Figure 14.1. UART0 Block Diagram ....................................................................... 127

Figure 14.2. UART0 Baud Rate Logic .................................................................... 128

Figure 14.3. UART Interconnect Diagram .............................................................. 129

Figure 14.4. 8-Bit UART Timing Diagram............................................................... 129

Figure 14.5. 9-Bit UART Timing Diagram............................................................... 130

Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 131

15. Timers

Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 140

Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 141

Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 142

Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 147

Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 148

16. Programmable Counter Array

Figure 16.1. PCA Block Diagram............................................................................ 151

Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 152

Figure 16.3. PCA Interrupt Block Diagram ............................................................. 153

Figure 16.4. PCA Capture Mode Diagram.............................................................. 154

Figure 16.5. PCA Software Timer Mode Diagram .................................................. 155

Figure 16.6. PCA High Speed Output Mode Diagram............................................ 156

Figure 16.7. PCA Frequency Output Mode ............................................................ 157

Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 158

Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 159

Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 160

17. C2 Interface

Figure 17.1. Typical C2 Pin Sharing....................................................................... 171

12

Rev. 2.6

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