UDA1344TS/N2 Просмотр технического описания (PDF) - Philips Electronics
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производитель
UDA1344TS/N2 Datasheet PDF : 28 Pages
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Philips Semiconductors
Low-voltage low-power stereo audio
CODEC with DSP features
Product specification
UDA1344TS
TIMING
VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages referenced to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
System clock input (see Fig.7)
Tsys
tCWH
tCWL
system clock cycle time
system clock HIGH time
system clock LOW time
fsys = 256fs
fsys = 384fs
fsys = 512fs
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
78
88
52
59
39
44
0.30Tsys −
0.40Tsys −
0.30Tsys −
0.40Tsys −
Serial interface input/output data (see Fig.8)
fBCK
Tcy(BCK)
bit clock frequency
bit clock cycle time
−
−
Tcy(s) = cycle time of
sample frequency
T----6c---y4--(-s---)
−
tBCKH
bit clock HIGH time
tBCKL
bit clock LOW time
tr
rise time
tf
fall time
tsu(WS)
word select set-up time
th(WS)
word select hold time
tsu(DATAI)
data input set-up time
th(DATAI)
data input hold time
th(DATAO)
data output hold time
td(DATAO−BCK) data output to bit clock delay
td(DATAO−WS) data output to word select delay
100
−
100
−
−
−
−
−
20
−
10
−
20
−
0
−
0
−
from BCK falling edge −
−
from WS edge for
−
−
MSB-justified format
L3 interface input (see Figs 4 and 5)
Tcy(CLK)L3
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
th(L3)A
tsu(L3)D
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time for address mode
L3MODE hold time for address mode
L3MODE set-up time for data transfer
mode
500
−
250
−
250
−
190
−
190
−
190
−
th(L3)D
tstp(L3)
tsu(L3)DA
L3MODE hold time for data transfer mode
L3MODE stop time
L3DATA set-up time in data transfer and
address mode
190
−
190
−
190
−
th(L3)DA
L3DATA hold time in data transfer and
address mode
30
−
−
ns
−
ns
−
ns
0.70Tsys ns
0.60Tsys ns
0.70Tsys ns
0.60Tsys ns
64fs
Hz
−
ns
−
ns
−
ns
20
ns
20
ns
−
ns
−
ns
−
ns
−
ns
−
ns
80
ns
80
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
2001 Jun 29
19
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