SAA56XX Просмотр технического описания (PDF) - Philips Electronics

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производитель

SAA56XX

Enhanced TV microcontrollers with On-Screen Display (OSD)

Philips Electronics 

Philips Semiconductors

Enhanced TV microcontrollers with

On-Screen Display (OSD)

Product specification

SAA56xx

BITS

FUNCTION

Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB)

P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 lines. For example, the

configuration of Port 0 pin 3 is controlled by setting bit 3 in both P0CFGA and

P0CFGB. P0CFGB<x>/P0CFGA<x>:

00 = P0.x in Mode 0 (open-drain)

01 = P0.x in Mode 1 (quasi-bidirectional)

10 = P0.x in Mode 2 (high-impedance)

11 = P0.x in Mode 3 (push-pull)

Port 1 Configuration A (P1CFGA) and Port 1 Configuration B (P1CFGB)

P1CFGA<7:0> and P1CFGB<7:0> These two registers are used to configure Port 1 lines. For example, the

configuration of Port 1 pin 3 is controlled by setting bit 3 in both P1CFGA and

P1CFGB. P1CFGB<x>/P1CFGA<x>:

00 = P1.x in Mode 0 (open-drain)

01 = P1.x in Mode 1 (quasi-bidirectional)

10 = P1.x in Mode 2 (high-impedance)

11 = P1.x in Mode 3 (push-pull)

Port 2 Configuration A (P2CFGA) and Port 2 Configuration B (P2CFGB)

P2CFGA<7:0> and P2CFGB<7:0> These two registers are used to configure Port 2 lines. For example, the

configuration of Port 2 pin 3 is controlled by setting bit 3 in both P2CFGA and

P2CFGB. P2CFGB<x>/P2CFGA<x>:

00 = P2.x in Mode 0 (open-drain)

01 = P2.x in Mode 1 (quasi-bidirectional)

10 = P2.x in Mode 2 (high-impedance)

11 = P2.x in Mode 3 (push-pull)

Port 3 Configuration A (P3CFGA) and Port 3 Configuration B (P3CFGB)

P3CFGA<7:0> and P3CFGB<7:0> These two registers are used to configure Port 3 lines. For example, the

configuration of Port 3 pin 3 is controlled by setting bit 3 in both P3CFGA and

P3CFGB. P3CFGB<x>/P3CFGA<x>:

00 = P3.x in Mode 0 (open-drain)

01 = P3.x in Mode 1 (quasi-bidirectional)

10 = P3.x in Mode 2 (high-impedance)

11 = P3.x in Mode 3 (push-pull)

Power Control Register (PCON)

SMOD

ARD

RFI

WLE

GF1

GF0

PD

IDL

UART baud rate double control

auxiliary RAM disable, all MOVX instructions access the external data memory

disable ALE during internal access to reduce radio frequency Interference

Watchdog Timer enable

general purpose flag

general purpose flag

Power-down activation bit

Idle mode activation bit

2001 Dec 13

20

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