AD7804 Просмотр технического описания (PDF) - Analog Devices

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AD7804

+3.3 V to +5 V Quad/Octal 10-Bit DACs

Analog Devices 

AD7804/AD7805/AD7808/AD7809

Table VI and Figure 22 show the analog outputs available for

the above configuration. The following is the procedure re-

quired if the complete transfer function needs to be offset

around the VBIAS point. Table VII and Figure 23 show the ana-

log output variations available from the Sub DAC.

System Control Register Write:

MODE = 0, address inputs (A2, A1, A0) are don’t cares.

Write 020 Hex Configure part for 10-bit parallel, twos

complement coding, normal operation

Channel Control Register Write:

MODE = 0, address inputs (A2, A1, A0) select desired channel.

Write 091 Hex

Internal VDD/2 selected as VBIAS for

DAC, and any DAC data writes that

follow are to the Sub DAC.

DAC Data Register Write:

MODE = 1, address inputs (A2, A1, A0) select desired channel.

Write XX Hex

With MODE = 1 all data writes are to

the selected DACs Sub DAC. XX is the

required data. 7F Hex will give zero scale

and 80 Hex will give full scale from the

Sub DAC.

Channel Control Register Write:

MODE = 0, address inputs (A2, A1, A0) select desired channel.

Write 011 Hex

Internal VDD/2 selected as VBIAS for

DAC, and any DAC data writes that

follow are to the Main DAC.

DAC Data Register Write:

MODE = 1, address inputs (A2, A1, A0) select desired channel.

Write XXX Hex With MODE = 1 all data writes are to

the selected Main DAC. XXX is the

required data. 1FF Hex will give zero

scale and 200 Hex will give full scale

from the DAC.

OFFSET BINARY CODING

Table VIII shows the offset binary transfer function for the Main

DAC.

Table VIII. Offset Binary Code Table for Main DAC

Digital Inputs

MSB . . . LSB

Analog Output

1111111111

1111111110

1000000001

1000000000

0111111111

0000000001

0000000000

VBIAS+1.875 × VBIAS(1023–512)/1024

VBIAS+1.875 × VBIAS(1022–512)/1024

VBIAS+1.875 × VBIAS/1024

VBIAS

VBIAS+1.875 × VBIAS(511–512)/1024

VBIAS+1.875 × VBIAS(1–512)/1024

VBIAS/16

NOTE: The span range is (30/16) × VBIAS = 1.875 × VBIAS

31

16

VBIAS

VBIAS

VBIAS

16

DAC INPUT CODE 000 001

1FF 200 201

3FE 3FF

Figure 25. Main DAC Output Voltage vs. DAC Input Codes

(HEX) for Offset Binary Coding

Figure 25 shows the Main DAC transfer function when offset

binary coding is used. With offset binary coding selected the

output voltage can be calculated as follows:

VOUT' = VBIAS + 1.875 × VBIAS × ((NA-512)/1024)

where NA is the decimal equivalent of the offset binary input

code. NA ranges from 0 to 1023.

Table IX shows the offset binary transfer function for the Sub

DAC. Figure 26 shows the Sub DAC transfer function for

offset binary coding. Any Sub DAC output voltage can be

expressed as:

VOUT" = VBIAS/16 × [(NB-128)/256]

where NB is the decimal equivalent of the offset binary input

code. NB ranges from 0 to 255.

–18–

REV. A

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