BD64550EFV Просмотр технического описания (PDF) - ROHM Semiconductor
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BD64550EFV Datasheet PDF : 17 Pages
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BD64550EFV
Technical Note
●Serial interface
16-bit 3-linear type serial interface (SDATA (pin 26), SCLK (pin 27), STROBE (pin 25)) is provided to set the operation and
the value of current limit. Data are sent to the internal shift register by falling edge of SCLK pin in the area L of STROBE pin.
Data of shift register are written in an appropriate address of internal memory of 2*15 bits by rising edge of STROBE pin
according to address data of D15.The input order of serial data is from D0 to D15.
Address data
D15
Word select
0
WORD_S
1
WORD_D
Memory data allocation
BIT
WORD_S
D0 Rohm_Reserve[2]
D1 Rohm_Reserve[1]
D2 Rohm_Reserve[0]
D3 OFF TIME_2[2]
D4 OFF TIME_2[1]
D5 OFF TIME_2[0]
D6 BLANK TIME_2[1]
D7 BLANK TIME_2[0]
D8 OFF TIME_1[2]
D9 OFF TIME_1[1]
D10 OFF TIME_1[0]
D11 BLANK TIME_1[1]
D12 BLANK TIME_1[0]
D13 MASK SELECT
D14 SWOFF
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WORD_D
Rohm_Reserve[11]
Rohm_Reserve[10]
Rohm_Reserve[9]
Rohm_Reserve[8]
Rohm_Reserve[7]
Rohm_Reserve[6]
Rohm_Reserve[5]
Rohm_Reserve[4]
Rohm_Reserve[3]
PWM_MODE_2
S_PHASE_2
S_ENABLE_2
PWM_MODE_1
S_PHASE_1
S_ENABLE_1
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The timing of serial report writing is shown in the right figure.
And the minimum timing of each is as follows:
A：SDATA setup time･･･････････････････
10nsec
B：SDATA hold time････････････････････
10nsec
C：Setup STROBE to SCLK falling edge･･
50nsec
D：SCLK low pulse width････････････････
25nsec
E：SCLK High pulse width･･･････････････
25nsec
F：Setup SCLK falling edge to STROBE･･･
25nsec
G：STROBE pulse width････････････････
50nsec
H：Setup RESET to SCLK Rising･････････
50µsec
H
RESET
STROBE
D
E
F
G
C
SCLK
SDATA
AB
D0
D1
D15
○RESET signal is an internal RESET signal and generated inside IC at the same timing of external RESET output.
○STROBE, SCLK and SDATA signals are input signals through external ASIC.
Fig.15 Serial Signal Input Timing
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6/16
2010.06 - Rev.A
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