PLL Description
• Full Integration
• Integer-N PLL with programmable loop bandwidth
•
“Fractional-VCO†” with fvco = 2/3 frf
– Reduces pulling from high-power on-chip PA
– Reduces transmitter LO feed-through
– Reduces receiver DC offsets due to self-mixing
• Automatic frequency control integrated into PLL
• PLL achieves PN of < -100dBc/Hz@30KHz offset withfrf = 5.24 GHz
PLL
1/2
†H. Darabi, et. al., ISSCC 2001
XO
3rd-LPF
3rd-LPF
Crystal
Clock out
AFC_I in
AFC_Q in