ATTINY87-MUR Просмотр технического описания (PDF) - Atmel Corporation

Номер в каталоге

Компоненты Описание

производитель

ATTINY87-MUR

8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

Atmel Corporation 

ATtiny87/ATtiny167

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This

can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the

internal BOD does not match the needed detection level, an external low VCC reset protection

circuit can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

3.4 I/O Memory

The I/O space definition of the ATtiny87/167 is shown in Section 24. “Register Summary” on

page 271.

All ATtiny87/167 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,

the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT,

the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space

using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny87/167 is a

complex microcontroller with more peripheral units than can be supported within the 64 loca-

tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from

0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can there-

fore be used on registers containing such Status Flags. The CBI and SBI instructions work

with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

3.4.1

General Purpose I/O Registers

The ATtiny87/167 contains three General Purpose I/O Registers. These registers can be used

for storing any information, and they are particularly useful for storing global variables and Sta-

tus Flags.

The General Purpose I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

3.5 Register Description

3.5.1

EEARH and EEARL – EEPROM Address Register

Bit

0x22 (0x42)

0x21 (0x41)

Bit

Read/Write

Read/Write

Initial Value

Initial Value

7

–

EEAR7

7

R

R/W

0

X

6

–

EEAR6

6

R

R/W

0

X

5

–

EEAR5

5

R

R/W

0

X

4

–

EEAR4

4

R

R/W

0

X

3

–

EEAR3

3

R

R/W

0

X

2

–

EEAR2

2

R

R/W

0

X

1

–

EEAR1

1

R

R/W

0

X

0

EEAR8

EEAR0

0

R/W

R/W

X

X

EEARH

EEARL

21

8265A–AVR–08/10

Share Link: