ATF1504BE Просмотр технического описания (PDF) - Atmel Corporation

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ATF1504BE

High-performance CPLD

Atmel Corporation 

Table 8-7. SSTL3-1 DC Voltage Specifications

Symbol

Parameter

Conditions

Min

Typ

VCCIO

VREF(1)

VTT(2)

Input Source Voltage

Input Reference Voltage

Termination Voltage

3.0

3.3

1.3

1.5

VREF - 0.05

1.5

VIH

Input High Voltage

VREF + 0.4

VIL

Input Low Voltage

-0.3

VOH

Output High Voltage

IOH = -8 mA, VCCIO = 3V

VCCIO - 1.1

VOL

Output Low Voltage

IOL = 8 mA, VCCIO = 2.3V

VIH(DC)

Input High Voltage

VREF + 0.18

VIL(DC)

Input Low Voltage

-0.3

Notes: 1. Peak-to-peak noise on VREF may not exceed ±2% VREF, VREF should track the variations in VCCIO.

2. VTT of transmitting device must track VREF of receiving devices.

Max

3.6

1.7

VREF + 0.05

VCCIO + 0.3

VREF - 0.6

0.7

VCCIO + 0.3

VREF - 0.18

Units

V

V

V

V

V

V

V

V

V

9. Timing Model

Input

Delay

tIN

(+tSCH)

Switch

Matrix

tUIM

Internal Output

Enable Delay

tIOE

Global Control

Delay

tGLOB

Logic Array

Delay

tLAD

Register

Control

Delay

tLAC tIC tEN

Foldback Term

Delay

tSEXP

Cascade Logic

Delay

tPEXP

Fast Input

Delay

tFIN

Register/

Combinatorial

Delays

tSUI

t

HI

tPRE

tCLR

tRD

tCOMB

tFSUI

tFHI

Output

Delay

tOD1

(+tSSO)

tXZ

t

ZX1

tZX2

(+SSTL2-1_OAD)

(+SSTL3-1_OAD)

I/O

Delay

tIO

(+tSCH)

(+SSTL2-1_IAD)

(+SSTL3-1_IAD)

18 ATF1504BE

3637B–PLD–1/08

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