AT90S8515 Просмотр технического описания (PDF) - Atmel Corporation

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AT90S8515

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90S8515

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt

flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt

enable bit, INT0 in GIMSK are set (one), the MCU will jump to the interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by

writing a logical “1” to it. This flag is always cleared when INT0 is configured as level

interrupt.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8515 and always read as zero.

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

6

5

4

3

2

1

0

$39 ($59)

TOIE1 OCIE1A OCIE1B

–

TICIE1

–

TOIE0

–

TIMSK

Read/Write

R/W

R/W

R/W

R

R/W

R

R/W

R

Initial Value

0

0

0

0

0

0

0

0

• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector

$006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set

in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at

vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the

OCF1A bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at

vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the

OCF1B bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt

(at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e.,

when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector

$007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set

in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

27

0841G–09/01

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