AT89S52-24AC Просмотр технического описания (PDF) - Atmel Corporation
Номер в каталоге
Компоненты Описание
производитель
AT89S52-24AC Datasheet PDF : 39 Pages
| |||
AT89S52
34. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
1.0
12 tCLCL
700
10 tCLCL-133
50
2 tCLCL-80
0
0
700
10 tCLCL-133
35. Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
CLOCK
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
0
1
2
3
4
5
6
7
8
tQVXH
0
tXHDV
VALID
tXLXL
tXHQX
1
VALID
2
tXHDX
VALID
3
VALID
4
VALID
5
VALID
6
7
SET TI
VALID
VALID
INPUT DATA
SET RI
Units
µs
ns
ns
ns
ns
36. AC Testing Input/Output Waveforms(1)
Note:
VCC - 0.5V
0.45V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
37. Float Waveforms(1)
Note:
VLOAD
V
+
LOAD
0.1V
V LOAD - 0.1V
Timing Reference
Points
V OL - 0.1V
V OL + 0.1V
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.
33
1919C–MICRO–3/05
Share Link: 