HI7131 Просмотр технического описания (PDF) - Intersil
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HI7131 Datasheet PDF : 21 Pages
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HI7131, HI7133
A worst case condition would be a large positive common-
mode voltage with a near full scale negative differential input
voltage. The negative input signal drives the integrator posi-
tive when most of its swing has been used up by the positive
common mode voltage. For these critical applications the
integrator output swing can be reduced to less than the rec-
ommended 2V full scale swing with little loss of accuracy.
The integrator output can swing to within 0.3V of either
supply without loss of linearity.
CINT
IN HI +-
RINT
+
-
VIN
IN LO
VINT
VCM (COMMON MODE VOLTAGE)
(V+ - V-)/2
AZ
INT.
V+
DEINT.
IN LO
positive signal but lose charge (decrease voltage) when
called up to deintegrate a negative input signal. This change
in reference for positive or negative input voltage will give a
rollover error. However, by selecting the reference capacitor
such that it is large enough in comparison to the stray capac-
itances, this error can be held to less than 0.5 counts worst
case. See the “Component Value Selection” section for
auto-zero capacitor value.
TEST Pin
The TEST pin serves two functions. It is coupled to the
internally generated digital ground through an effective 500Ω
resistor. Thus, it can be used as the digital ground for external
digital circuits such as segment drivers for decimal points or
any other annunciator the user may want to include on the
LCD display. For these applications the external digital circuit
should be supplied between V+ and TEST pin. Figures 9 and
10 show such an application. In Figure 9 a MOSFET transis-
tor is used to invert the BP signal to drive the decimal point.
The MOSFET can be any general purpose type with a thresh-
old voltage less than 3.5V and ON resistance less than 500Ω.
Figure 10 uses an CMOS IC XOR gate to generate controlla-
ble decimal point drives. No more than a 1mA load should be
applied to TEST pin by any external digital circuitry.
V-
V+
IN LO
NORMAL INTEGRATOR OUTPUT
WAVEFORM (NEGATIVE INPUT)
AZ
INT.
DEINT.
V+
HI7131/33
BP 21
TEST
37
1MΩ
TO LCD
DECIMAL
POINT
TO LCD
BACKPLANE
V-
INTEGRATOR OUTPUT WITH IN LO TOO
CLOSE TO POSITIVE SUPPLY RAIL (NEGATIVE INPUT)
FIGURE 97. SIMPLE INVERTER FOR FIXED DECIMAL POINT
DRIVE
FIGURE 96. COMMON MODE VOLTAGE CONSIDERATION
Differential Reference (REF HI, REF LO) and Reference
Capacitor Pins (CREF+, CREF-)
As was discussed in the analog section (Figure 5), the differ-
ential reference pins are connected across the reference
capacitor (connected to pins CREF+ and CREF-) to charge it
during the zero integrate and the auto-zero phase. Then the
reference capacitor is used as either a positive or negative
reference during the deintegrate phase. The reference
capacitor acts as a flying capacitor between the reference
voltage and integrator inputs in the deintegrate phase.
The common mode voltage range for the reference inputs is
V+ to V-. The reference voltage can be generated anywhere
within the power supply range of the converter. The main
source of rollover error is reference common mode voltage
caused by the reference capacitor losing or gaining charge
to or from stray capacitance on its nodes. If there is a large
common mode voltage, the reference capacitor can gain
charge (increase voltage) when called upon to deintegrate a
V+
V+
BP
HI7131/33
DECIMAL
POINT
SELECT
TO LCD
DECIMAL
POINTS
TEST
CD4070B
GND
FIGURE 98. EXCLUSIVE “OR” GATE FOR DECIMAL POINTS
AND ANNUNCIATORS DRIVE
The second function of the TEST pin is the “lamp test”.
When the TEST pin is pulled high (to V+) all segments will
be turned on and the display should read -1888. The test pin
will sink about 10mA under these conditions.
CAUTION: In the lamp test mode, the segments have a constant DC
voltage (no square-wave). This may burn the LCD display if
maintained for extended periods.
3-1839
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