HI7133CM44 Просмотр технического описания (PDF) - Intersil
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HI7133CM44 Datasheet PDF : 21 Pages
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HI7131, HI7133
1. Figure 7A, an External Oscillator Driving OSC 1.
2. Figure 7B, an RC Oscillator Using All 3 Oscillator Circuit
Pins.
INTERNAL TO PART
÷4
CLOCK
40
39
38
TEST
FIGURE 95A. EXTERNAL SIGNAL
INTERNAL TO PART
÷4
CLOCK
40
39
38
R
C
The total length of a conversion cycle is equal to 4000
counts and is independent of the input signal magnitude or
full scale range. Each phase of the conversion cycle has the
following length:
Auto-Zero Phase
100 counts in case an overrange is detected. 990 to 2990
counts for normal conversion. For those inputs which are less
than full scale, the deintegrate length is less than 2000 counts.
Those extra counts on deintegrate phase are assigned to
auto-zero phase to keep the conversion cycle constant.
Signal Integrate Phase
1000 counts, a fixed period of time. The time of integration
can be calculated as:
TINT = 1000f--C---1--L---K-- = 4000-f-O----1-S----C--.
Deintegrate Phase
0 to 2000 counts, variable length phase depending on the
input voltage.
Zero Integrate Phase
10 counts in case of normal conversion. 900 counts in case
an overrange is detected.
FIGURE 95B. RC OSCILLATOR
FIGURE 95. CLOCK CIRCUITS
The oscillator output frequency is divided by 4 before it clocks
the rest of the digital section. Notice that there are 2 separate
frequencies which are referred to as; oscillator frequency
(fOSC) and clock frequency (fCLK) with the relation of:
fCLK
=
f--O-----S----C--
4
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. For 60Hz,
rejection oscillator frequencies of 120kHz, 80kHz, 60kHz,
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40kHz, etc. would be suitable. Note that 40kHz (2.5 read-
ings/sec) will reject both 50Hz and 60Hz (also 400Hz and
440Hz).
For the RC oscillator configuration the relationship between
oscillator frequency, R and C values are:
fOSC ≈ -R----O-----S--0--C-.--4-C--5--O-----S----C--
(R in Ohms and C in Farads.)
System Timing
As it has been mentioned, the oscillator output is divided by
4 prior to clocking the digital section and specifically, the
internal decade counters. The control logic looks at the
counter outputs and comparator output (see analog section)
to form the appropriate timing for 4 phases of conversion
cycle.
Functional Considerations of Device Pins
COMMON Pin
The COMMON pin is the device internal reference generator
output.
The COMMON pin sets a voltage that is about 2.8V less
than the V+ supply rail. This voltage (V+ - VCOMMON) is the
on-chip reference which can be used for setting converter
reference voltage.
Within the IC, the COMMON pin is tied to an N-Channel tran-
sistor capable of sinking up to 3mA of current and still keeping
COMMON voltage within the range. However, there is only 1µA
of source current capability. The COMMON pin can be used as
a virtual ground in single supply applications when the external
analog signals need a reference point in between the supply
rails. If higher sink and source current capability is needed for
virtual ground a unity gain op-amp can be used as a buffer.
Differential Inputs (IN LO, IN HI)
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
1V below the positive supply to 1V above the negative supply.
In this range, the system has a CMRR of 120dB (Typ).
However, care must be exercised to assure the integrator
output does not saturate. This is illustrated in Figure 8, which
shows how common mode voltage affects maximum swing on
the integrator output. Figure 8 shows the circuit configuration
during conversion. In this figure, common mode voltage is
considered as a voltage on the IN LO pin referenced to
(V+ - V-) / 2, which is usually the GND in a dual supply
system.
3-1838
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