AS6C62256 Просмотр технического описания (PDF) - Alliance Semiconductor

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AS6C62256

32K X 8 BIT LOW POWER CMOS SRAM

Alliance Semiconductor 

February 2007

AS6C62256

®

32K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER

VCC for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL

TEST CONDITION

VDR CE# ≧ VCC - 0.2V

IDR

VCC = 2.0V

CE# ≧ VCC - 0.2V

tCDR

See Data Retention

Waveforms (below)

tR

DATA RETENTION WAVEFORM

Vcc

CE#

Vcc(min.)

tCDR

VIH

VDR ≧ 2.0V

CE# ≧ Vcc-0.2V

MIN.

2.0

-

0

tRC*

TYP.

-

0.5

-

-

MAX.

5.5

20

-

-

UNIT

V

µA

ns

ns

Vcc(min.)

tR

VIH

02/FEB/07, v1.0

Alliance Memory Inc.

Page 7 of 12

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