AS3932 Просмотр технического описания (PDF) - austriamicrosystems AG
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AS3932 Datasheet PDF : 33 Pages
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AS3932
Data Sheet - Detailed Description
The AGC can operate in two modes:
AGC down only (R1<5>=0)
AGC up and down (R1<5>=1)
As soon as the AGC starts to operate, the gain in the VGA is set to maximum. If the AGC down only mode is selected, the AGC can only
decrease the gain. Since the RSSI is directly derived from the VGA gain, the system holds the RSSI peak.
When the AGC up and down mode is selected, the RSSI can follow the input signal strength variation in both directions.
Regardless which AGC operation mode is used, the AGC needs maximum 35 carrier periods to settle.
The RSSI is available for all 3 channels at the same time and it is stored in 3 registers (R10<4:0>, R11<4:0>, R12<4:0>)
Both AGC modes (only down or down and up) can also operate with time limitation. This option allows AGC operation only in time slot of 256µs
following the internal wake-up. Then the AGC (RSSI) is frozen till the wake-up or RSSI reset occurs.
The RSSI is reset either with the direct command 'clear_wakeup' or 'reset_RSSI'. The 'reset_RSSI' command resets only the AGC setting but
does not terminate wake-up condition. This means that if the signal is still present the new AGC setting (RSSI) will appear not later than 300µs
(35 LF carrier periods) after the command was received. The AGC setting is reset if for duration of 3 Manchester half symbols no carrier is
detected. If the wake-up IRQ is cleared the chip will go back to listening mode.
In case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller starting gain on the
amplifier, according to the Table 14. In this way it is possible to reduce the false frequency detection.
Table 14. Bit Setting of Gain Reduction
R4<3>
R4<2>
R4<1> R4<0>
Gain reduction
0
0
0
0
no gain reduction
0
0
0
1
n.a.
0
0
1
0 or 1
n.a.
0
1
0
0 or 1
-4dB
0
1
1
0 or 1
-8dB
1
0
0
0 or 1
-12dB
1
0
1
0 or 1
-16dB
1
1
0
0 or 1
-20dB
1
1
1
0 or 1
-24dB
8.4.2 Antenna Damper
The antenna damper allows the chip to deal with higher field strength, it is enabled by register R1<4>. It consists of shunt resistors which
degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. In this way the resonator sees a smaller parallel
resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amplifier (the amplifier
doesn't saturate in presence of bigger signals). Table 15 shows the bit setup.
Table 15. Antenna Damper Bit Setup
R4<5>
R4<4>
Shunt resistor (parallel to the resonator at 125 kHz)
0
0
1 kΩ
0
1
3 kΩ
1
0
9 kΩ
1
1
27 kΩ
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Revision 1.2
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