AS1154 Просмотр технического описания (PDF) - austriamicrosystems AG

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AS1154

Single/Dual LVDS Driver

austriamicrosystems AG 

AS1156/AS1154

Data Sheet - Package Drawings and Markings

10 Package Drawings and Markings

The AS1156/AS1154 is available in a 8-pin SOIC package.

Figure 23. 8-pin SOIC Package

Notes:

1. Lead coplanarity should be 0 to 0.10mm (.004”) max.

2. Package surface finishing:

- Top, matte (charmilles #18-30)

- All sides, matte (charmilles +18-30)

- Bottom, smooth or matte (charmilles +18-30)

3. All dimensions excluding mold flashes and end flash from the pack-

age body shall not exceed 0.25mm (.010”) per side.

4. Details of pin #1 mark are optional but must be located within the

area indicated.

Symbol

A

A1

A2

B

C

D

E

e

H

h

L

α

ZD

Min

Max

1.52

1.72

0.10

0.25

1.37

1.57

0.36

0.46

0.19

0.25

4.80

4.98

3.81

3.99

1.27BSC

5.80

6.20

0.25

0.50

0.41

1.27

0º

8º

0.53REF

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Revision 1.01

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