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MR27V3266D Просмотр технического описания (PDF) - Oki Electric Industry

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Компоненты Описание
производитель
MR27V3266D
OKI
Oki Electric Industry OKI
MR27V3266D Datasheet PDF : 36 Pages
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1 Semiconductor
AC CHARACTERISTICS FOR SYNCHRONOUS READ ( 1/2 )
MR27V3266D
Parameter
Symbol
Min
Max
CLK Cycle time
tCC
15
-
Data to Valid Output Delay
tAC
-
9
Data Output Hold Time
tOH
3
-
CLK High Pulse Width
tCH
4
-
CLK Low Pulse Width
tCL
4
-
Input Setup Time
tSI
3
-
Input Hold Time
tHI
1.5
-
CLK to Output in Low-Z
tOLZ
0
-
CLK to Output in High-Z
tOHZ
-
10
Input Level Transition Time
tT
0.1
10
"Row Active" to "Read" Delay Time
tRCD
1CLK
-
2CLK
-
"Read" to "Row Active" delay
( Words of preceding "Read"
CL = 4
BL = 4
CL = 5
tCRD
tCRD
3CLK
4CLK
-
-
command can be read )
< Random Access >
CL = 4 tCRD
3CLK
-
BL = 8
CL = 5 tCRD
4CLK
-
"Read" to "Read" delay
( Words of preceding "Read"
CL = 4
BL = 4
CL = 5
tCCD
tCCD
3CLK
4CLK
-
-
command can be read )
< Sequential Access >
CL = 4 tCCD
3CLK
-
BL = 8
CL = 5 tCCD
4CLK
-
"Row Active" Cycle Time
( Words of preceding "Read"
CL = 4 tRC 3CLK + tRCD
-
BL = 4
CL = 5 tRC 4CLK + tRCD
-
command can be read )
< Random Access >
CL = 4 tRC 3CLK + tRCD
-
BL = 8
CL = 5 tRC 4CLK + tRCD
-
"Read" to "Read" delay
( Gapless burst read )
CL = 4 tCCD
4CLK
-
BL = 4
CL = 5 tCCD
4CLK
-
< Sequential Access >
CL = 4 tCCD
8CLK
-
BL = 8
CL = 5 tCCD
8CLK
-
"Read" to "Burst Stop" Delay
1CLK
-
"Read" to "Precharge" Delay
1CLK
-
Power Down Exit Setup Time
tPDE
tSI + 1CLK
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Notes
2
1,2
1
1,2
1
1,2
1
1,2
1
1,2
1
1,2
1
2
1
2
Note
1. Shortage of clock cycles interrupt the data sensing of preceding "Read" command.
The shortage of cycle time for preceding command is detected by internal command controller to cease
the preceding command operation.
The latest "Row Active" or "Read" command is completed.
When legal tCCD is shorter than BL, burst read is terminated with another burst read.
2. Up to 50MHz
August , 1999
Revision 2.4
32M Synchronous OTP
14

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