CXA1787N Просмотр технического описания (PDF) - Sony Semiconductor

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CXA1787N

2GHz-band PLL IC for Mobile Communications

Sony Semiconductor 

CXA1787N

Description of Operation

1. Data Setting Method

The data is set using three signals — CK, DATA, and LAT in this IC.

In that case, the serial data as described below is input.

(1) Data input method

The 15 bits of data should be input to the reference counter latch and the 18 bis of data to the pulse swallow

programmable counter latch to set the all initializing state in this IC. Every one bit of data is retrieved into the

shift resister at the rising edge of clock input to the CK pin when the data is input to the DATA pin. The input

data is retrieved into the reference counter latch or the pulse swallow programmable counter latch according to

the state of the final bit C.

The data is latched when the latch pulse is input to the LAT pin after 16 bits of data or 19 bits of data, which

were added with the bit C, are sent to the shift resister.

For actual use, first input the 16 bits (including the frequency division setting bit SW for 2-modulus prescaler) of

reference counter data from the controller as indicated above. In this time, set the final bit C High.

Next, input the 19 bits of pulse swallow programmable counter data in the same way. In this time, set the final

bit C Low. Then, all of the interior state has been set. Hereafter, when only the programmable counter data is

to be changed, only the latter 19 bits of programmable counter data should be changed. (In this case, set the

bit C Low.)

(2) Control data construction

The control data consists of 16 bits for the reference counter and 19 bits for the pulse swallow programmable

counter. The final bit of them is the identification code and the contents of data are discriminated by identifying

the code. The frequency division value is composed of the binary values whose head is MSB as described on

the next page.

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