AOZ1025D Просмотр технического описания (PDF) - Alpha and Omega Semiconductor

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AOZ1025D

EZBuck™ 8A Synchronous Buck Regulator

Alpha and Omega Semiconductor 

AOZ1025D

Thermal Management and Layout

Consideration

In the AOZ1025 buck regulator circuit, the major power

dissipating components are the AOZ1025 output

inductor, and low-side NMOSFET. The total power

dissipation of converter circuit can be measured by

input power minus output power:

Ptotal_loss = VIN  IIN – VO  IO

The power dissipation of inductor can be approximately

calculated by output current and DCR of inductor:

Pinductor_loss = IO2  Rinductor  1.1

The power dissipation of low-side NMOSFET can be

approximately calculated by output current, Rdson, and

duty cycle (VO / VIN).

Pinductor_loss

=

IO2



Rinduc

to

r









1

–

V-V----IO-N--

The actual junction temperature can be calculated with

power dissipation in the AOZ1025 and thermal

impedance from junction to ambient.

Several layout tips are listed below for the best electric

and thermal performance:

1. Do not use thermal relief connection to the VIN and

the PGND pin. Pour a maximized copper area to

the PGND pin and the VIN pin to help thermal

dissipation.

2. Input capacitor should be connected to the VIN pin

and the PGND pin as close as possible.

3. A ground plane is preferred. If a ground plane is not

used, separate PGND from AGND and connect them

only at one point to avoid the PGND pin noise

coupling to the AGND pin.

4. Make the current trace from LX pins to L to Co to the

PGND as short as possible.

5. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, PGND or

SGND.

6. Keep sensitive signal trace away from switching

node, LX. The copper pour area connected to the

LX pin should be as wide as possible to avoid the

switching noise on the LX pin coupling to other part

of circuit.

Tjunction = Ptotal_loss – Pinductor_loss – Pnmos_loss  JA + Tamb

The thermal performance of the AOZ1025D is strongly

affected by the PCB layout. Extra care should be taken

by users during design to ensure that the IC will operate

under the recommended environmental conditions.

Rev. 1.4 June 2012

Figure 3. AOZ1025D (DFN 5x4) PCB Layout

www.aosmd.com

Page 11 of 15

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