AM79C961AVCW Просмотр технического описания (PDF) - Advanced Micro Devices

Номер в каталоге

Компоненты Описание

производитель

AM79C961AVCW

PCnet™-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

IRQ 3, 4, 5, 9, 10, 11, 12, 15

Interrupt Request

Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, MISS, MERR,

RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.

All status flags have a mask bit which allows for sup-

pression of IRQ assertion. These flags have the

following meaning:

BABL

RCVCCO

JAB

MISS

MERR

MPCO

RINT

IDON

TXDATSTRT

Babble

Receive Collision Count Overflow

Jabber

Missed Frame

Memory Error

Missed Packet Count Overflow

Receive Interrupt

Initialization Done

Transmit Start

Because of the operation of the Plug and Play regis-

ters, the interrupts on the PCnet-ISA II must be

attached to specific IRQ signals on the PC/AT bus.

LA17-23

Unlatched Address Bus

Input/Output

The unlatched address bus is driven by the PCnet-ISA

II controller during bus master cycle.

The functions of these unlatched address pins will

change when GPSI mode is invoked. The following

table shows the pin configuration in GPSI mode. Please

refer to the section on General Purpose Serial Interface

for detailed information on accessing this mode.

Pin

Number

10

11

12

13

15

16

17

Pin Function in Bus

Master Mode

LA17

LA18

LA19

LA20

LA21

LA22

LA23

Pin Function in

GPSI Mode

RXDAT

SRDCLK

RXCRS

CLSN

STDCLK

TXEN

TXDAT

MASTER

Master Mode

Input/Output

This signal indicates that the PCnet-ISA II controller

has become the Current Master of the ISA bus. After

the PCnet-ISA II controller has received a DMA

Acknowledge (DACK) in response to a DMA Request

(DRQ), the Ethernet controller asserts the MASTER

signal to indicate to the Permanent Master that the PC-

net-ISA II controller is becoming the Current Master.

MEMR

Memory Read

Input/Output

MEMR goes LOW to perform a memory read operation.

MEMW

Memory Write

Input/Output

MEMW goes LOW to perform a memory write

operation.

REF

Memory Refresh

Input

When REF is asserted, a memory refresh is active. The

PCnet-ISA II controller uses this signal to mask inad-

vertent DMA Acknowledge assertion during memory

refresh periods. If DACK is asserted when REF is

active, DACK assertion is ignored. REF is monitored to

eliminate a bus arbitration problem observed on some

ISA platforms.

RESET

Reset

Input

When RESET is asserted HIGH the PCnet-ISA II con-

troller performs an internal system reset. RESET must

be held for a minimum of 10 XTAL1 periods before

being deasserted. While in a reset state, the PCnet-ISA

II controller will tristate or deassert all outputs to pre-

defined reset levels. The PCnet-ISA II controller resets

itself upon power-up.

SA0-19

System Address Bus

Input/Output

This bus contains address information, which is stable

during a bus operation, regardless of the source.

SA17-19 contain the same values as the unlatched

address LA17-19. When the PCnet-ISA II controller is

the Current Master, SA0-19 will be driven actively.

When the PCnet-ISA II controller is not the Current

Master, the SA0-19 lines are continuously monitored to

determine if an address match exists for I/O slave

transfers or Boot PROM accesses.

SBHE

System Byte High Enable

Input/Output

This signal indicates the high byte of the system data

bus is to be used. SBHE is driven by the PCnet-ISA II

controller when performing bus mastering operations.

SD0-15

System Data Bus

Input/Output

These pins are used to transfer data to and from the

PCnet-ISA II controller to system resources via the ISA

data bus. SD0-15 is driven by the PCnet-ISA II control-

Am79C961A

19

Share Link: