AM79C02 Просмотр технического описания (PDF) - Advanced Micro Devices

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производитель

AM79C02

Dual Subscriber Line Audio Processing Circuit (DSLAC™) Devices

Advanced Micro Devices 

Master Clock

For 2.048 MHz ±100 ppm or 4.096 MHz ±100 ppm operation:

No. Symbol

Parameter

35

tMCY Master Clock Period (2.048 MHz)

Master Clock Period (4.096 MHz)

36

tMCR Rise Time of Clock

37

tMCF Fall Time of Clock

38

tMCH MCLK High Pulse Width (2.048 MHz)

MCLK High Pulse Width (4.096 MHz)

39

tMCL MCLK Low Pulse Width (2.048 MHz)

MCLK Low Pulse Width (4.096 MHz)

Min

488.23

244.11

200

80

200

80

Typ

488.28

244.14

15

Max

488.33

244.17

Units

15

ns

Notes:

1. DCLK may be stopped in the High or Low state indefinitely without loss of information. If CS makes a transition to the Low

state, the last byte received is interpreted by the Microprocessor Interface logic.

2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK

frequency. The actual PCLK rate is dependent on the number of channels allocated within a frame. The DSLAC supports 2–

128 channels. A PCLK of 1.544 MHz can be used for standard US transmission systems. The minimum clock frequency is

128 kHz.

3. TSC is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock-slot register.

4. There is a special conflict detection circuitry that prevents high-power dissipation from occurring when the DXA or DXB pins

of two DSLAC devices are tied together and one DSLAC device starts to transmit before the other has gone into a high-

impedance state.

5. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.

6. tTSO is defined as the time at which the output achieves the open circuit condition.

7. The DSLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed

while the MCLK input is not active, a Chip Select Off time of 20 µs is required.

SWITCHING WAVEFORMS

Input and Output Waveforms for AC Tests

2.4

2.0

Test

2.0

0.8

Points

0.8

0.45

Master Clock Timing

35

38

VIH

VIL

39

37

36

09875H-012

09875H-013

18

Am79C02/03/031(A) Data Sheet

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