NT256S64VH8A0GM-8B Просмотр технического описания (PDF) - Nanya Technology
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NT256S64VH8A0GM-8B
Nanya Technology
NT256S64VH8A0GM-8B Datasheet PDF : 12 Pages
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NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
Operating, Standby, and Refresh Currents (TA =0 to 70 °C, VDD =3.3 ± 0.3V)
Parameter
Symbol
Test condition
Speed
Unit
- 7K - 75B - 8B
1 bank operation , tRC = tRC(mim), tCK = min
Operating current
ICC1
Active-Precharge Command cycling
without burst operation
1040
960
920
mA
Precharge
standby current
in power-down mode
ICC2P
ICC2PS
Precharge
standby current in non
power-down mode
ICC2N
ICC2NS
No Operating current
( Active state : 4 bank)
ICC3P
ICC3N
Operating current
( Burst mode )
ICC4
CKE ≤ VIL (max), tCK = min,
S0 , S1= VIH (min)
CKE ≤ VIL (max), tCK =oo,
S0 , S1= VIH (min)
CKE ≥ VIH (min), tCK = min
S0 , S1= VIH (min)
CKE ≥ VIH (min), tCK =oo,
S0 , S1= VIH (min)
CKE ≤ VIL (max), tCK =min.
S0 , S1= VIH (min) , (Power Down Mode)
CKE ≥ VIH (min), tCK =min
S0 , S1= VIH (min)
tCK =min , Read/ Write command cycling,
Multiple banks active, gapless data, BL=4
16
mA
16
mA
240
240
160
mA
64
64
64
mA
48
48
48
mA
480
480
360
mA
960
960
720
mA
Auto(CBR)
refresh current
ICC5
tCK =min, CBR command cycling
1400 1400 1320
mA
Self refresh current
ICC6
CKE ≤ 0.2V
24
mA
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC . Input
signals are changed up to three times during t RC (min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during tCK(min) .
7. VDD =3.3V
Note
1, 2
3
4
5
3
2, 6
PRELIMINARY 08 / 2001
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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