μPD43256B
Write Cycle Timing Chart 1 (/WE Controlled)
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
Indefinite data out
High
impe-
dance
tOW
tDW
tDH
Data in
High
impe-
dance
Indefinite data out
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
Data Sheet M10770EJEV0DS
15