AL710 Просмотр технического описания (PDF) - AverLogic Technologies Inc

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AL710

QUAD Video Processor

AverLogic Technologies Inc 

AL700/701/710

<NA>: Non-Acknowledged stage

The host (master) generates acknowledge-related clock pulse. The host also releases the

SDA line (to High) during the acknowledge clock pulse, but the AL700/701/710 does not

pull it down during this stage.

<Data>: Data byte written to or read from the register index

In read operation, the host must release the SDA line (to High) before the first clock pulse

is transmitted to the AL700/701/710.

<P>: Stop signal

SCL

High

SDA

Low to High

The Stop signal appears at Low to High transition on the SDA line when SCL is High.

Suppose data F0h is to be written to register 0Fh using write slave address 70h, the timing

is as follows:

Start Slave a ddr = 70h Ack Ind ex = 0Fh Ack Data = F0h Ack Stop

SDA

SCL

Figure 3: I2C Serial Bus Write Timing

Suppose data is to be read from register 55h using read slave address 71h, the timing is as

follows:

Start

Ack

R e ad slave a ddr = 71h

NAck

Slave addr = 70h

Ind ex = 55h Ack Start

Ack Data re a d cycle

Stop

SDA

SCL

Figure 4: I2C Serial Bus Read Timing

©2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 16

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