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ADV7611BSWZ-P

Low Power 165 MHz HDMI Receiver

Analog Devices 

Data Sheet

ADV7611

GENERAL DESCRIPTION

The ADV7611 is offered in automotive, professional (no

HDCP), and industrial versions. The operating temperature

range is −40oC to +85oC.

The UG-180 contains critical information that must be used in

conjunction with the ADV7611.

The following audio formats are accessible:

• A stream from the I2S serializer (two audio channels)

• A stream from the S/PDIF serializer (two uncompressed

channels or N compressed channels, for example, AC3)

• DST stream

The ADV7611 is a high quality, single input HDMI®-capable

receiver. It incorporates an HDMI-capable receiver that

supports all mandatory 3D TV defined in HDMI 1.4a. The

ADV7611 supports formats up to UXGA 60 Hz at 8 bit.

It integrates a CEC controller that supports the capability

discovery and control (CDC) feature.

The ADV7611 has an audio output port for the audio data

extracted from the HDMI stream. The HDMI receiver has an

advanced mute controller that prevents audible extraneous

noise in the audio output.

The HDMI port has dedicated 5 V detect and Hot Plug™ assert

pins. The HDMI receiver also includes an integrated equalizer

that ensures the robust operation of the interface with long cables.

The ADV7611 contains one main component processor (CP),

that processes the video signals from the HDMI receiver. It

provides features such as contrast, brightness and saturation

adjustments, STDI detection block, free run, and synchronization

alignment controls.

Fabricated in an advanced CMOS process, the ADV7611 is

provided in a 10 mm × 10 mm, 64-lead surface-mount LQFP_EP,

RoHS-compliant package and is specified over the −40°C to

+85°C temperature range.

DETAILED FUNCTIONAL BLOCK DIAGRAM

XTALP

XTALN

SCL

SDA

CEC

RXA_5V

HPA_A/INT2*

DDCA_SDA

DDCA_SCL

RXA_C±

RXA_0±

RXA_1±

RXA_2±

DPLL

CEC

CONTROLLER

5V DETECT

AND HPD

CONTROLLER

EDID

REPEATER

CONTROLLER

PLL

CONTROL

INTERFACE

I2C

CONTROL

AND DATA

HDMI

PROCESSOR

HDCP

EEPROM

DATA

PREPROCESOR

AND COLOR

SPACE

CONVERSION

EQUALIZER

SAMPLER

HDCP

ENGINE

PACKET

PROCESSOR

12

12

12

BACKEND

COLORSPACE

CONVERSION

COMPONENT

PROCESSOR

A

B

C

INTERRUPT

CONTROLLER

(INT1,INT2)

PACKET/

INFOFRAME

MEMORY

MUTE

AUDIO

PROCESSOR

P0 TO P7

P8 TO P15

P16 TO P23

LLC

HS

VS/FIELD/ALSB

DE

INT1

INT2*

AP

LRCLK

SCLK/INT2*

MCLK/INT2*

*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.

Figure 2. Detailed Functional Block Diagram

ADV7611

Rev. D | Page 3 of 16

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