ADV7611BSWZ Просмотр технического описания (PDF) - Analog Devices
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ADV7611BSWZ Datasheet PDF : 16 Pages
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ADV7611
Data Sheet
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7611 is highly flexible. The pixel
output bus can support up to 24-bit 4:4:4 YCrCb. The pixel data
supports both single and double data rates modes. In SDR mode, a
16-/24-bit 4:2:2 or 24-bit 4:4:4 output is possible. In DDR mode1,
the pixel output port can be configured in an 8-/12-bit 4:2:2 YCrCb
or 24-bit 4:4:4 RGB.
Bus rotation is supported. Table 5 and Table 6 outline the different
output formats that are supported. All output modes are controlled
via I2C.
1 DDR mode is only supported only up to 50 MHz (an equivalent to data rate
clocked 100 MHz clock in SDR mode).
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include:
• 8-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD output signals
• 16-/24-bit YCrCb with embedded time codes and/or HS
and VS/FIELD pin timing
• 24-bit YCrCb/RGB with embedded time codes and/or HS
and VS/FIELD pin timing
• DDR 8-/12-bit 4:2:2 YCrCb
• DDR 24-bit 4:4:4 RGB
Table 5. SDR 4:2:2 and 4:4:4 Output Modes
OP_FORMAT_SEL[7:0]
Pixel Output
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
0x01
8-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x0A1
12-Bit SDR
ITU-R BT.656
Mode 2
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
SDR 4:2:2
0x80
16-Bit SDR
ITU-R BT.656 4:2:2
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
0x8A
24-Bit SDR
ITU-R BT.656 4:2:2
Mode 2
Y3
Y2
Y1
Y0
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Cb11, Cr11
Cb10, Cr10
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
1 Modes 0x00 and 0x0A require additional writes to IO Map Register 0x19[7:6] = 2’b11 and IO Map Register 0x33[6] = 1
SDR 4:4:4
0x40
24-Bit SDR 4:4:4
Mode 0
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
Rev. D | Page 12 of 16
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