ADXL375 Просмотр технического описания (PDF) - Analog Devices
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ADXL375 Datasheet PDF : 32 Pages
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ADXL375
I2C MODE
When the CS pin is tied high to VDD I/O, the ADXL375 is
configured for I2C mode. I2C mode requires a simple 2-wire
connection, as shown in Figure 28. The ADXL375 conforms to
the UM10204 I2C-Bus Specification and User Manual, Rev. 03—
19 June 2007, available from NXP Semiconductors. The ADXL375
supports standard (100 kHz) and fast (400 kHz) data transfer
modes if the bus parameters given in Table 13 and Table 14 are met.
Single- or multiple-byte reads and writes are supported, as shown
in Figure 29. When the ALT ADDRESS pin (Pin 12) is tied high
to VDD I/O, the 7-bit I2C address for the device is 0x1D, followed
by the R/W bit. In this configuration, the write address is 0x3A,
and the read address is 0x3B. An alternate I2C address of 0x53 can
be selected by grounding the ALT ADDRESS pin (see Figure 28).
In this configuration, the write address is 0xA6, and the read
address is 0xA7.
Unused pins have no internal pull-up or pull-down resistors;
therefore, the CS and ALT ADDRESS pins have no known state
or default state if the pins are left floating or unconnected. When
using I2C mode, it is required that the CS pin be connected to
VDD I/O and that the ALT ADDRESS pin be connected to either
VDD I/O or GND.
Data Sheet
VDD I/O
ADXL375
RP
CS
SDA
ALT ADDRESS
SCL
RP PROCESSOR
D IN/OUT
D OUT
Figure 28. I2C Connection Diagram (Address 0x53)
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I2C mode is 800 Hz, which scales
linearly with a change in the I2C communication speed. For
example, using I2C mode at 100 kHz limits the maximum ODR
to 200 Hz. Operation at an output data rate above the recom-
mended maximum value may result in undesirable effects on the
acceleration data, including missing samples or additional noise.
If other devices are connected to the same I2C bus, the nominal
operating voltage level of the other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary
for proper I2C operation (see Figure 28). To ensure proper opera-
tion, refer to the UM10204 I2C-Bus Specification and User Manual,
Rev. 03—19 June 2007, when selecting pull-up resistor values.
SINGLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
STOP
ACK
MULTIPLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
ACK
DATA
SINGLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
MULTIPLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
1THIS START IS EITHER A REPEATED START OR A STOP FOLLOWED BY A START.
NOTES
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 29. I2C Device Addressing
STOP
ACK
DATA
NACK STOP
DATA
ACK
DATA
Table 13. I2C Digital Input/Output Specifications
Parameter
DIGITAL INPUT
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
DIGITAL OUTPUT
Low Level Output Voltage (VOL)
Low Level Output Current (IOL)
PIN CAPACITANCE
Test Conditions/Comments
VS = VDD I/O
VS = 0 V
VDD I/O < 2 V, IOL = 3 mA
VDD I/O ≥ 2 V, IOL = 3 mA
VOL = VOL, MAX
fIN = 1 MHz, VS = 2.5 V
Limit1
Min
Max
0.7 × VDD I/O
−0.1
0.3 × VDD I/O
0.1
0.2 × VDD I/O
400
3
8
1 Limits based on characterization results; not production tested.
NACK STOP
Unit
V
V
µA
µA
V
mV
mA
pF
Rev. 0 | Page 18 of 32
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