ADXL312(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADXL312 Datasheet PDF : 32 Pages
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Data Sheet
ADXL312
REGISTER DEFINITIONS
Register 0x00—DEVID (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
0
0
1
0
1
The DEVID register holds a fixed device ID code of 0xE5.
Register 0x1E, Register 0x1F, Register 0x20—OFSX,
OFSY, OFSZ (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and
offer user-set offset adjustments in twos complement format
with a scale factor of 11.6 mg/LSB (that is, 0x7F = +1.5 g). The
value stored in the offset registers is automatically added to the
acceleration data, and the resulting value is stored in the output
data registers.
Register 0x24—THRESH_ACT (Read/Write)
The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned;
therefore, the magnitude of the activity event is compared with
the value in the THRESH_ACT register. The scale factor is
46.4 mg/LSB. A value of 0 may result in undesirable behavior if
the activity interrupt is enabled.
Register 0x25—THRESH_INACT (Read/Write)
The THRESH_INACT register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned;
therefore, the magnitude of the inactivity event is compared
with the value in the THRESH_INACT register. The scale factor is
46.4 mg/LSB. A value of 0 may result in undesirable behavior if
the inactivity interrupt is enabled.
Register 0x26—TIME_INACT (Read/Write)
In dc-coupled operation, the current acceleration magnitude is
compared directly with THRESH_ACT and THRESH_INACT
to determine whether activity or inactivity is detected.
In ac-coupled operation for activity detection, the acceleration
value at the start of activity detection is taken as a reference
value. New samples of acceleration are then compared to this
reference value and, if the magnitude of the difference exceeds
the THRESH_ACT value, the device triggers an activity interrupt.
Similarly, in ac-coupled operation for inactivity detection, a
reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the
difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.
ACT_x Enable Bits and INACT_x Enable Bits
A setting of 1 enables x-, y-, or z-axis participation in detecting
activity or inactivity. A setting of 0 excludes the selected axis
from participation. If all axes are excluded, the function is
disabled. For activity detection, all participating axes are
logically OR’ed, causing the activity function to trigger when
any of the participating axes exceeds the threshold. For inactiv-
ity detection, all participating axes are logically AND’ed, causing
the inactivity function to trigger only if all participating axes are
below the threshold for the specified period of time.
Register 0x2C—BW_RATE (Read/Write)
D7 D6 D5 D4
D3 D2 D1 D0
0 0 0 LOW_POWER
Rate
The TIME_INACT register is eight bits and contains an unsigned
time value representing the amount of time that acceleration
must be less than the value in the THRESH_INACT register for
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
the other interrupt functions, which use unfiltered data (see the
Threshold section), the inactivity function uses filtered output
data. At least one output sample must be generated for the
inactivity interrupt to be triggered. This results in the function
appearing unresponsive if the TIME_INACT register is set to a
value less than the time constant of the output data rate. A value
of 0 results in an interrupt when the output data is less than the
value in the THRESH_INACT register.
Register 0x27—ACT_INACT_CTL (Read/Write)
D7
D6
D5
D4
ACT ac/dc ACT_X enable ACT_Y enable ACT_Z enable
D3
D2
D1
D0
INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable
ACT AC/DC and INACT AC/DC Bits
A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation.
LOW_POWER Bit
A setting of 0 in the LOW_POWER bit selects normal operation,
and a setting of 1 selects reduced power operation, which has
somewhat higher noise (see the Power Modes section for details).
Rate Bits
These bits select the device bandwidth and output data rate (see
Table 6 and Table 7 for details). The default value is 0x0A, which
translates to a 100 Hz output data rate. An output data rate must
be selected that is appropriate for the communication protocol
and frequency selected. Selecting too high of an output data rate
with a low communication speed results in samples being
discarded.
Register 0x2D—POWER_CTL (Read/Write)
D7 D6 D5 D4
D3
D2 D1 D0
0 0 Link AUTO_SLEEP Measure Sleep Wakeup
Link Bit
A setting of 1 in the link bit with both the activity and inactivity
functions enabled delays the start of the activity function until
inactivity is detected. After activity is detected, inactivity detection
begins, preventing the detection of activity. This bit serially links
the activity and inactivity functions.
Rev. B | Page 21 of 32
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