ADXL312WACPZ-RL(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADXL312WACPZ-RL Datasheet PDF : 32 Pages
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ADXL312
SERIAL COMMUNICATIONS
The ADXL312 can communicate via I2C and SPI digital
communications interfaces. In both cases, the ADXL312 operates
as a slave. If I2C is the desired interface for the application, tie
the CS pin directly to VDDI/O as shown in Figure 27. If SPI is the
desired interface for the application, drive the CS pin with an
external controller, as demonstrated in Figure 21 and Figure 22.
Because the I2C interface is enabled any time the CS pin is brought
up to VDD I/O, there is a potential for bus conflicts to occur when the
ADXL312 is implemented into a SPI network. Refer to the
Preventing Bus Traffic Errors section for information on how to
avoid such conditions. In both SPI and I2C modes of operation,
ignore data transmitted from the ADXL312 to the master device
during writes to the ADXL312.
Note that throughout this section, multifunction pins, such as
SDA/SDI/SDIO, are referred to either by the entire pin name or
by a single function of the pin, for example, SDA, when only
that function is relevant.
SERIAL PORT I/O DEFAULT STATES
Ensure that all serial port I/Os are in a defined state and that no
pin is allowed to float when not in use. This is applicable to all
serial port I/Os, regardless of SPI or I2C operation.
For I2C applications, always tie the CS pin high to VDD I/O.
Connect the SCL and SDA pins to an external controller, with
pull-up resistors implemented according to the UM10204 I2C-
Bus Specification and User Manual, Rev. 03—19 June 2007,
available from NXP Semiconductor. The ALT ADDRESS pin
must be tied to either VDD I/O or ground, thereby selecting the
desired I2C address for the ADXL312.
If SPI is the intended communications interface, drive the CS
pin with an external controller, as shown in Figure 21 and
Figure 22. When communications with the ADXL312 are
suspended (CS = VDD I/O), ensure that the SCLK, SDI/SDIO, and
SDO pins are not floating.
For either SPI or I2C operation, not taking these precautions may
result in an inability to communicate with the device or excessive
current consumption.
SPI
For the SPI, either 3- or 4-wire configuration is possible, as shown
in the connection diagrams in Figure 21 and Figure 22. Clearing
the SPI bit in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
the ADXL312 before the clock polarity and phase of the host
processor are configured, bring the CS pin high before changing
the clock polarity and phase.
Data Sheet
When using 3-wire SPI, pull the SDO pin up to VDD I/O or down
to ground via a 10 kΩ resistor, as shown in Figure 21.
CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at
the end of a transmission, as shown in Figure 24. SCLK is the
serial port clock and is supplied by the SPI master. SDI and
SDO are the serial data input and output, respectively.
ADXL312
PROCESSOR
CS
SDIO
SDO
SCLK
D_OUT
D_IN/OUT
D_OUT
RPD
Figure 21. 3-Wire SPI Connection Diagram
ADXL312
CS
SDI
SDO
SCLK
PROCESSOR
D_OUT
D_OUT
D_IN
D_OUT
Figure 22. 4-Wire SPI Connection Diagram
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/W bit in the first byte transfer
(MB in Figure 24 to Figure 26), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL312 to point
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads
or writes on different nonsequential registers, CS must be
deasserted between transmissions, and the new register must be
addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 26. The 4-wire equivalents for SPI writes and reads are
shown in Figure 24 and Figure 25, respectively. For correct opera-
tion of the device, the logic thresholds and timing parameters in
Table 8 and Table 9 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only
recommended with SPI communication rates greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only for communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
below the recommended minimum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
Rev. B | Page 12 of 32
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