ADT7490(2016) Просмотр технического описания (PDF) - ON Semiconductor
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ADT7490 Datasheet PDF : 75 Pages
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ADT7490
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted) (Note 1)
Parameter
Digital Input Logic Levels (TACH1 to TACH3)
Conditions
Min
Typ
Max
Unit
Input High Voltage, VIH
Maximum Input Voltage
2.0
−
−
V
−
−
5.5
Input Low Voltage, VIL
Minimum Input Voltage
−
−
0.8
V
−0.3
−
−
Hysteresis
−
0.5
−
V p-p
Digital Input Logic Levels (THERM)
Input High Voltage, VIH
Input Low Voltage, VIL
Digital Input Current
0.75 × VCCP
−
−
−
−
V
0.4
V
Input High Current, IIH
VIN = VCC
Input Low Current, IIL
VIN = 0
Input Capacitance, CIN
Serial Bus Timing (Note 2) (See Figure 2)
−
±1
−
mA
−
±1
−
mA
−
5.0
−
pF
Clock Frequency, fSCLK
10
−
400
kHz
Glitch Immunity, tSW
−
−
50
ns
Bus Free Time, tBUF
4.7
−
−
ms
SCL Low Time, tLOW
4.7
−
−
ms
SCL High Time, tHIGH
4.0
−
50
ms
SCL, SDA Rise Time, tr
−
−
1,000
ns
SCL, SDA Fall Time, tf
−
−
300
ms
Data Setup Time, tSU;DAT
250
−
−
ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15
−
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.
2. Guaranteed by design, not production tested.
3. VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system.
SCL
SDA
tBUF
P
S
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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