ADSP-21992BST Просмотр технического описания (PDF) - Analog Devices
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ADSP-21992BST Datasheet PDF : 60 Pages
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ADSP-21992
Table 7. Recommended Operating Conditions—ADSP-21992BST
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
VDDEXT
AVDD
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
2.375
2.5
2.625
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
HCLK1, 2
Peripheral Clock Rate
0
CLKIN3
Input Clock Frequency
0
TJUNC4
Silicon Junction Temperature
TAMB
Ambient Operating Temperature
–40
160
MHz
80
MHz
160
MHz
140
ЊC
+85
ЊC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK،2, up to a maximum of a 80 MHz HCLK for the ADSP-21992BST.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Table 8. Recommended Operating Conditions—ADSP-21992YST
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
VDDEXT
AVDD
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
2.375
2.5
2.625
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
HCLK1, 2
Peripheral Clock Rate
0
CLKIN3
Input Clock Frequency
0
TJUNC4
Silicon Junction Temperature
TAMB
Ambient Operating Temperature
–40
100
MHz
50
MHz
100
MHz
140
ЊC
+125
ЊC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK،2, up to a maximum of an 50 MHz HCLK for the ADSP-21992YST.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Rev. A | Page 21 of 60 | August 2007
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