ADSP-2196MKCA-160X Просмотр технического описания (PDF) - Analog Devices

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ADSP-2196MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2196

Table 22. JTAG Port Timing

JTAG Test And Emulation Port Timing

Table 22 and Figure 26 describe JTAG port operations.

Parameter Description

Min

Max

Unit

Switching Characteristics

tDTDO

tDSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low1

Timing Parameters

4

ns

0

5

ns

tTCK

TCK Period

20

ns

tSTAP

TDI, TMS Setup Before TCK High

4

ns

tHTAP

tSSYS

tHSYS

tTRSTW

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low2

System Inputs Hold After TCK Low2

TRST Pulsewidth3

4

ns

4

ns

5

ns

4

ns

1System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,

TFS0, TFS1, RFS0, RFS1, BMS.

2System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,

CLKIN, RESET.

350 MHz max.

7&.

706

7',

7'2

6<67(0

,138 76

6<67(0

2873876

W7&.

W67$3

W+7$3

W'7'2

W6 6 < 6

W+6<6

W'6<6

Figure 26. JTAG Port Timing

REV. PrA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

51

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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