ADSP-21469KBCZ-3(Rev0) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21469KBCZ-3
(Rev.:Rev0)

SHARC Processor

Analog Devices 

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 45 on Page 58 under Test Conditions for voltage refer-

ence levels.

In the following sections, Switching Characteristics specify how

the processor changes its signals. Circuitry external to the pro-

cessor must be designed for compatibility with these signal

characteristics. Switching characteristics describe what the pro-

cessor will do in a given circumstance. Use switching

characteristics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

In the following sections, Timing Requirements apply to signals

that are controlled by circuitry external to the processor, such as

the data input for a read operation. Timing requirements guar-

antee that the processor operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

fVCO specified in Table 18.

• The product of CLKIN and PLLM must never exceed 1/2 of

fVCO (max) in Table 18 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed

fVCO (max) in Table 18 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

fVCO = 2 × PLLM × fINPUT

fCCLK = (2 × PLLM × fINPUT) ÷ (PLLD)

where:

fVCO = VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

ADSP-21469

PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value

programmed on the PMCTL register. During reset this value

is 2.

fINPUT = input frequency to the PLL

fINPUT = CLKIN when the input divider is disabled, or

fINPUT = CLKIN  2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in and

Table 16. All of the timing specifications for the ADSP-21469

peripherals are defined in relation to tPCLK. See the peripheral

specific section for each peripheral’s timing information.

Table 16. Clock Periods

Timing

Requirements

tCK

tCCLK

tPCLK

Description

CLKIN Clock Period

Processor Core Clock Period

Peripheral Clock Period = 2 × tCCLK

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-214xx SHARC Processor Hard-

ware Reference.

Rev. 0 | Page 21 of 72 | June 2010

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