ADP5023(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADP5023 Datasheet PDF : 28 Pages
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Data Sheet
ADP5023
THEORY OF OPERATION
VOUT1 FB1 FB2 VOUT2
AVIN
VIN1
SW1
GM ERROR
AMP
ENBK1 75Ω
PWM
COMP
SOFT START
ILIMIT
LOW
CURRENT
PWM/
PSM
CONTROL
BUCK1
PSM
COMP
75Ω
ENBK2
GM ERROR
AMP
ADP5023
SOFT START
PWM
COMP
PSM
COMP
ILIMIT
PWM/
PSM
CONTROL
BUCK2
LOW
CURRENT
PGND1
DRIVER
AND
ANTISHOOT
THROUGH
OSCILLATOR
SYSTEM
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
DRIVER
AND
ANTISHOOT
THROUGH
OPMODE
SEL B MODE2
Y
A
VIN2
SW2
PGND2
MODE
LDO
UNDERVOLTAGE
LOCK OUT
EN1
ENBK1
R1
ENABLE
EN2
AND MODE
ENBK2
CONTROL
ENLDO
EN3
VDDA
LDO
CONTROL
R2
600Ω ENLDO
VIN3
AGND FB3 VOUT3
Figure 45. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5023 is a micropower management unit (micro PMU)
combining two step-down (buck) dc-to-dc converters and one
low dropout linear regulator (LDO). The high switching
frequency and tiny 24-lead LFCSP package allows a small
power management solution.
To combine these high performance regulators into the micro
PMU, there is a system controller allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at a logic
low level, the switching regulators operate in auto PWM/PSM
mode. In this mode, the regulators operate at fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator in question enters PSM, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses. The auto PWM/PSM mode transition is
controlled independently for each buck regulator. The two
bucks operate synchronized to each other.
The ADP5023 has individual enable pins (EN1 to EN3) control-
ling the activation of each regulator. The regulators are activated
by a logic level high applied to the respective EN pin. EN1 controls
BUCK1, EN2 controls BUCK2, and EN3 controls LDO.
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled though a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators.
Extreme junction temperatures can be the result of high current
Rev. A | Page 17 of 28
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