ADP5023(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADP5023
(Rev.:RevA)

Dual 3 MHz, 800 mA Buck Regulators with One 300 mA LDO

Analog Devices 

ADP5023

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by

PSW

=

(CGATE-P

+

CGATE-N)

×

V2

IN1

×

fSW

(10)

where:

CGATE-P is the P-MOSFET gate capacitance.

CGATE-N is the N-MOSFET gate capacitance.

For the ADP5023, the total of (CGATE-P + CGATE-N) is

approximately 150 pF.

The transition losses occur because the P-channel power

MOSFET cannot be turned on or off instantaneously, and the

SW node takes some time to slew from near ground to near

VOUT1 (and from VOUT1 to ground). The amount of transition

loss is calculated by

PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW

(11)

where tRISE and tFALL are the rise time and the fall time of the

switching node, SW. For the ADP5023, the rise and fall times of

SW are in the order of 5 ns.

If the preceding equations and parameters are used for estimat-

ing the converter efficiency, it must be noted that the equations

do not describe all of the converter losses, and the parameter

values given are typical numbers. The converter performance

also depends on the choice of passive components and board

layout; therefore, a sufficient safety margin should be included

in the estimate.

LDO Regulator Power Dissipation

The power loss of a LDO regulator is given by

PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND)

(12)

where:

ILOAD is the load current of the LDO regulator.

VIN and VOUT are input and output voltages of the LDO,

respectively.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is small and it

can be ignored.

The total power dissipation in the ADP5023 simplifies to

PD = PDBUCK1 + PDBUCK2 + PDLDO

(13)

Data Sheet

JUNCTION TEMPERATURE

In cases where the board temperature TA is known, the thermal

resistance parameter, θJA, can be used to estimate the junction

temperature rise. TJ is calculated from TA and PD using the

formula

TJ = TA + (PD × θJA)

(14)

The typical θJA value for the 24-lead, 4 mm × 4 mm LFCSP is

35°C/W (see Table 6). A very important factor to consider is

that θJA is based on 4-layer, 4 in × 3 in, 2.5 oz copper, as per

JEDEC standard, and real applications may use different sizes

and layers. It is important to maximize the copper used to remove

the heat from the device. Copper exposed to air dissipates heat

better than copper used in the inner layers. The exposed pad

should be connected to the ground plane with several vias.

If the case temperature can be measured, the junction

temperature is calculated by

TJ = TC + (PD × θJC)

(15)

where TC is the case temperature and θJC is the junction-to-case

thermal resistance provided in Table 6.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5023 power

dissipation (PD) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, TJ, can be estimated using Equation 14.

The reliable operation of the converter and the two LDO regulators

can be achieved only if the estimated die junction temperature of

the ADP5023 (Equation 14) is less than 125°C. Reliability and

mean time between failures (MTBF) is highly affected by increas-

ing the junction temperature. Additional information about

product reliability can be found from the ADI Reliability Handbook,

which can be found at www.analog.com/reliability_handbook.

Rev. A | Page 16 of 28

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