ADP3025 Просмотр технического описания (PDF) - Analog Devices

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ADP3025

High Efficiency Dual Output Power Supply Controller

Analog Devices 

ADP3025

CURRENT LIMITING (CLSET)

POWER GOOD OUTPUT (PWRGD)

A cycle-by-cycle current limiting scheme is used by monitoring

The ADP3025 also provides a PWRGD signal output. During

current through the top N-channel MOSFET when it is turned

startup, the PWRGD pin is held low until the 5 V output is

on. By measuring the voltage drop across the high-side

within –3% of its preset voltage. Then, after a time delay

MOSFET, VDS(ON), the use of an external sense resistor can be

determined by an external timing capacitor connected from

omitted. The current limit value can be set by CLSET. When

CPOR to GND, PWRGD is actively pulled up to INTVCC by an

CLSET is floating, the maximum VDS(ON) = 72 mV at room

external pull-up resistor. This delay can be calculated by

temperature; when CLSET = 0 V, the maximum VDS(ON) =

300 mV at room temperature. An external resistor can be

connected between CLSET and AGND to choose a value

1.2 V × CCPOR

t D = 1 μA

(2)

between 72 mV and 300 mV. The relationship between the

external resistance and the maximum VDS(ON) is

(110 kΩ + REXT)

VDS(ON )MAX = 72 mV

(1)

(26 kΩ + REXT)

E The temperature coefficient of RDS(ON) of the N-channel

MOSFET is canceled by the internal current limit circuitry, so

an accurate current limit value can be obtained over a wide

T temperature range.

OUTPUT UNDERVOLTAGE PROTECTION

Each switching controller has an undervoltage protection

E circuit. When the current flowing through the high-side

MOSFET reaches the current limit continuously for eight clock

cycles and the output voltage stays below 20% of the nominal

L output voltage, both controllers are latched off and do not

restart until SD or SS3/SS5 is toggled, or until VIN is cycled

below 4.05 V. This feature is disabled during soft start.

OUTPUT OVERVOLTAGE AND REVERSE VOLTAGE

O PROTECTION

Both converter outputs are continuously monitored for

overvoltage. If either output voltage is higher than the nominal

S output voltage by more than 20%, both converters’ high-side

gate drivers (DRVH5/3) are latched off, and the low-side gate

drivers are latched on. The chip will not restart until SD or

SS5/SS3 is toggled, or until VIN is cycled below 4.05 V. The low-

B side gate driver (DRVL) is kept high when the controller is in

the off-state and the output voltage is less than 93% of the

nominal output voltage. Discharging the output capacitors

O through the main inductor and low-side N-channel MOSFET

CPOR can also be used as a manual reset (MR) input. When the

5 V output is lower than the preset voltage by more than 7%,

PWRGD is immediately pulled low.

LINEAR REGULATOR CONTROLLER

The ADP3025 includes an on-board linear regulator controller.

An external NMOS can be used as the pass transistor. The

output voltage can be set by a resistor divider. The minimum

output voltage of the LDO is 800 mV, while the maximum

output voltage cannot exceed a voltage level determined by the

IC’s INTVCC voltage minus the threshold voltage of the

external

N-type MOSFET device. Assuming a INTVCC of 5 V, the

recom-mended maximum output voltage is around 2.5 V. To

ensure loop stability, a compensation network can be attached

to the COMP2/SD2 pin, as shown in Figure 17.

Large signal response limits the maximum/minimum load ratio.

When the linear regulator is loaded, the MOSFET’s gate source

voltage is at its threshold level and changes only slightly. The

loop response speed depends on the loop transfer function,

which is fast enough for most applications. However, when the

load is extremely light, the gate source voltage of the MOSFET

is much lower than its nominal value. If at this moment the load

increases suddenly, the MOSFET’s gate source capacitance

needs to be charged up, which takes time. To optimize large

signal response, not exceeding a maximum-to-minimum load

ratio of 100 to 1 is recommended.

causes the output to ring. This makes the output go below GND

momentarily. To prevent damage to the circuit, use a 1 A

Schottky diode in parallel with the output capacitors to clamp

the negative surge.

Rev. A | Page 12 of 24

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