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ADN4663BRZ

Dual, 3 V, CMOS, LVDS High Speed Differential Driver

Analog Devices 

THEORY OF OPERATION

The ADN4663 is a dual line driver for low voltage differential

signaling. It takes a single-ended 3 V logic signal and converts

it to a differential current output. The data can then be transmitted

for considerable distances, over media such as a twisted-pair cable

or PCB backplane, to an LVDS receiver, where it develops a voltage

across a terminating resistor, RT. This resistor is chosen to match

the characteristic impedance of the medium, typically around

100 Ω. The differential voltage is detected by the receiver and

converted back into a single-ended logic signal.

When DINx is high (Logic 1), current flows out of the DOUTx+ pin

(current source) through RT and back into the DOUTx− pin (current

sink). At the receiver, this current develops a positive differential

voltage across RT (with respect to the inverting input) and results

in a Logic 1 at the receiver output. When DINx is low, DOUTx+

sinks current and DOUTx− sources current; a negative differential

voltage across RT results in a Logic 0 at the receiver output.

The output drive current is between ±2.5 mA and ±4.5 mA

(typically ±3.55 mA), developing between ±250 mV and ±450 mV

across a 100 Ω termination resistor. The received voltage is centered

around the receiver offset of 1.2 V. Therefore, the noninverting

receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and

the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V

for Logic 1. For Logic 0, the inverting and noninverting output

voltages are reversed. Note that because the differential voltage

reverses polarity, the peak-to-peak voltage swing across RT is

twice the differential voltage.

Current mode drivers offer considerable advantages over

voltage mode drivers such as RS-422 drivers. The operating

current remains fairly constant with increased switching

frequency, whereas that of voltage mode drivers increase

exponentially in most cases. This is caused by the overlap

as internal gates switch between high and low, which causes

currents to flow from the device power supply to ground.

ADN4663

A current mode device simply reverses a constant current

between its two outputs, with no significant overlap currents.

This is similar to emitter-coupled logic (ECL) and positive

emitter-coupled logic (PECL), but without the high quiescent

current of ECL and PECL.

APPLICATIONS INFORMATION

Figure 21 shows a typical application for point-to-point data

transmission using the ADN4663 as the driver and a LVDS

receiver.

0.1µF

VCC

+3.3V

+ 10µF

TANTALUM

+3.3V

+

VCC

DINx

ADN4663

DOUTx+

RT

100Ω

DOUTx–

DIN+

DIN–

LVDS RECEIVER

DOUT

GND

GND

Figure 21. Typical Application Circuit

Rev. 0 | Page 11 of 12

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