ADN4612 Просмотр технического описания (PDF) - Analog Devices
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ADN4612 Datasheet PDF : 76 Pages
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ADN4612
Data Sheet
ELECTRICAL SPECIFICATIONS—CONTROL LOGIC PINS
Table 3.
Parameter
I2C LOGIC CHARACTERISTICS
Input
High
Low
Output
High
Low
Symbol Test Conditions/Comments
Min
Typ
VIH
DVCC = 1.8 V
VIL
DVCC = 1.8 V
0.7 × DVCC
VEE
VOH
I2C only, 2 kΩ pull-up resistor to DVCC
DVCC
IOH = −1 mA
0.8 × DVCC
VOL
IOL = +1 mA
VEE
I2C MASTER AND SLAVE TIMING SPECIFICATIONS
Table 4.
Parameter1
SCL2 CLOCK FREQUENCY
Master Interface
Slave Interface
START CONDITION
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
SCL2 CLOCK
Low Period
High Period
DATA (SDA3)
Data Hold Time
Data Setup Time
SDA3 AND SCL2
Rise Time
Fall Time
SETUP TIME FOR STOP CONDITION
BUS TIME
Bus Free Time Between a Stop Condition and a Start Condition
Bus Idle Time After Reset
Symbol Test Conditions/Comments
fSCL
Load from EEPROM only
fSCL
tHD;STA
tSU;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
1 Detailed functionality of the I2C interface is described in the I2C Serial Control Interface section.
2 SCL is the I2C serial clock function of the SCK/SCL pin.
3 SDA is the I2C serial data function of the SDO/SDA pin.
I2C Timing Diagram
Max
Unit
DVCC
V
0.3 × DVCC V
V
DVCC
V
0.2 × DVCC V
Min Max Unit
0
100 kHz
0
400 kHz
0.6
μs
0.6
μs
1.3
μs
0.6
μs
0
μs
10
ns
1
300 ns
1
300 ns
0.6
μs
1
ns
10
ns
SDA
tF
SCL
S
tLOW
tSU;DAT
tR
tHD;STA
tHD;DAT
tF
tHD;STA
tHIGH
tSU;STA
Sr
Figure 2. I2C Timing Diagram
tSP
tR
tBUF
tSU;STO
P
S
Rev. C | Page 6 of 76
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