ADM6996F Просмотр технического описания (PDF) - Infineon Technologies

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ADM6996F

6 port 10/100 Mb/s Single Chip Ethernet Switch Controller

Infineon Technologies 

ADM6996F

Function Description

3.4.4

Data De-scrambling

The de-scrambler acquires synchronization with the data stream by recognizing idle

bursts of 40 or more bits and locking its deciphering Linear Feedback Shift Register

(LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the

incoming data is XORed by the deciphering LFSR and de-scrambled.

In order to maintain synchronization, the de-scrambler continuously monitors the validity

of the unscrambled data that it generates. To ensure this, a link state monitor and a hold

timer are used to constantly monitor the synchronization status. Upon synchronization of

the de-scrambler the hold timer starts a 722 us countdown. Upon detection of sufficient

idle symbols within the 722 us period, the hold timer will reset and begin a new

countdown. This monitoring operation will continue indefinitely given a properly

operating network connection with good signal integrity. If the link state monitor does

not recognize sufficient unscrambled idle symbols within 722 us period, the de-scrambler

will be forced out of the current state of synchronization and reset in order to re-acquire

synchronization.

3.4.5

Symbol Alignment

The symbol alignment circuit in the ADM6996F determines code word alignment by

recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de-

scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is

aligned on a fixed boundary.

3.4.6

Symbol Decoding

The symbol decoder functions as a look-up table that translates incoming 5B symbols

into 4B nibbles as shown in Table 1. The symbol decoder first detects the /J/K symbol

pair preceded by idle symbols and replaces the symbol with MAC preamble. All

subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of

the entire packet. This conversion ceases upon the detection of the /T/R symbol pair

denoting the end of stream delimiter (ESD). The translated data is presented on the

internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the

translated nibble.

3.4.7

Valid Data Signal

The valid data signal (RXDV) indicates that recovered and decoded nibbles are being

presented on the internal RXD[3:0] synchronous to receive clock, RXCLK. RXDV is

asserted when the first nibble of translated /J/K is ready for transfer over the internal MII.

It remains active until either the /T/R delimiter is recognized, link test indicates failure, or

no signal is detected. On any of these conditions, RXDV is de-asserted.

Infineon-ADMtek Co Ltd.

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