ADM1178 Просмотр технического описания (PDF) - Analog Devices

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ADM1178

Hot Swap Controller and Digital Power Monitor with ALERTB Output

Analog Devices 

ADM1178

When the initial timing cycle terminates, the device is ready to

start a hot swap operation (assuming that the ON pin is asserted).

In the example shown in Figure 33, the ON pin is asserted at the

same time as VCC is applied; therefore, the hot swap operation

starts immediately after Time Point 4. At this point, the FET

gate is charged up with a 12.5 µA current source.

At Time Point 5, the threshold voltage of the FET is reached and

the load current begins to flow. The FET is controlled to keep

the sense voltage at 100 mV (this corresponds to a maximum load

current level defined by the value of RSENSE).

At Time Point 6, VGATE and VOUT have reached their full potential,

and the load current has settled to its nominal level. Figure 34

illustrates the situation where the ON pin is asserted after VCC is

applied.

(1) (2)

(3)(4) (5)

(6)

VCC

VON

VTIMER

VGATE

VSENSE

VOUT

INITIAL TIMING

CYCLE

Figure 33. Startup (ON Asserts as Power Is Applied)

(1) (2)

Data Sheet

(3) (4)

(5)(6)

(7)

VCC

VON

VTIMER

VGATE

VSENSE

VOUT

INITIAL TIMING

CYCLE

Figure 34. Startup (ON Asserts After Power Is Applied)

HOT SWAP RETRY CYCLE ON THE ADM1178-1

With the ADM1178-1, the device turns off the FET after an

overcurrent fault and then uses the TIMER pin to time a delay

before automatically retrying to hot swap.

As with all ADM1178 devices, an overcurrent fault is timed by

charging the TIMER capacitor with a 60 μA pull-up current.

When the TIMER pin reaches 1.3 V, the fault current limit time

is reached, and the GATE pin is pulled down. On the ADM1178-1,

the TIMER pin is then pulled down with a 2 μA current sink.

When the TIMER pin reaches 0.2 V, it automatically restarts the

hot swap operation.

The cooldown period is related to CTIMER by Equation 8.

tCOOL ≈ 550 × CTIMER ms/μF

(8)

Therefore, the retry duty cycle is as given by Equation 9.

tFAULT/(tCOOL + tFAULT) × 100% = 3.8%

(9)

Rev. D | Page 14 of 24

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