ADM1030ARQ Просмотр технического описания (PDF) - Analog Devices

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ADM1030ARQ

Intelligent Temperature Monitor and PWM Fan Controller

Analog Devices 

ADM1030

Effect of ADC Sample Rate on Filtered Mode

The second means by which to change the Filtered Mode char-

acteristics is to adjust the ADC sample rate. The faster the ADC

sample rate, the more temperature samples are obtained per

second. One way to apply filtering to the control loop is to

slow down the ADC sampling rate. This means that the num-

ber of iterations of the Filtered Mode algorithm per second

are effectively reduced. If the number of temperature measure-

ments per second are reduced, how often the PWM_OUT

signal controlling the fan is updated is also reduced.

Bits <4:2> of the Fan Filter Register (Reg 0x23) set the ADC

sample rate. The default ADC sample rate is 1.4 kHz. The

ADC sample rate is selectable from 87.5 Hz to 11.2 kHz.

Table IX shows how many temperature samples are obtained

per second, for each of the ADC sample rates.

Table IX. Temperature Updates per Second

ADC Sample Rate

87.5 Hz

175 Hz

350 Hz

700 Hz

1.4 kHz

2.8 kHz

5.6 kHz

11.2 kHz

Temperature Updates/Sec

0.0625

0.125

0.25

0.5

1 (Default)

2

4

8

RELEVANT REGISTERS FOR FILTERED AUTOMATIC

FAN SPEED CONTROL MODE

In addition to the registers used to program the normal Auto-

matic Fan Speed Control Mode, the following register needs to

be programmed.

Register 0x23 Fan Filter Register

<7> Spin-up Disable :- when this bit is set to 1, fan spin-up

is disabled. (Default = 0)

<6:5> Ramp Rate: these bits set the ramp rate for filtered mode.

00 = 1 (0.416% Duty Cycle Change)

01 = 2 (0.833% Duty Cycle Change)

10 = 4 (1.66% Duty Cycle Change)

11 = 8 (3.33% Duty Cycle Change)

<4:2> ADC Sample Rate

000 = 87.5 Hz

001 = 175 Hz

010 = 350 Hz

011 = 700 Hz

100 = 1.4 kHz (Default)

101 = 2.8 kHz

110 = 5.6 kHz

111 = 11.2 kHz

<1> Unused. Default = 0

<0> Fan 1 Filter Enable: when this bit is set to 1, it enables

filtering on Fan 1. Default = 0.

PROGRAMMING THE FILTERED AUTOMATIC FAN

SPEED CONTROL LOOP

1. Program a value for TMIN.

2. Program a value for the slope TRANGE.

3. TMAX = TMIN + TRANGE.

4. Program a value for Fan Spin-up Time.

5. Program the desired Automatic Fan Speed Control Mode

Behavior, i.e., which temperature channel controls the fan.

6. Program a ramp rate for the filtered mode.

7. Program the ADC sample rate in the Fan Filter Register.

8. Set Bit 0 to enable fan filtered mode for the fan.

9. Select Automatic Fan Speed Control Mode by setting Bit 7 of

Configuration Register 1.

PWM DUTY CYCLE SELECT MODE

The ADM1030 may be operated under software control by clear-

ing Bit 7 of Configuration Register 1 (Register 0x00). This

allows the user to directly control PWM Duty Cycle.

Clearing Bit 5 of Configuration Register 1 allows fan control by

varying PWM duty cycle. Values of duty cycle between 0% to

100% may be written to the Fan Speed Config Register (0x22)

to control the speed of the fan. Table X shows the relationship

between hex values written to the Fan Speed Configuration

Register and PWM duty cycle obtained.

Table X. PWM Duty Cycle Select Mode

Hex Value

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

PWM Duty Cycle

0%

7%

14%

20%

27%

33%

40%

47%

53%

60%

67%

73%

80%

87%

93%

100%

–18–

REV. A

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