ADJD-S313-QR999 Просмотр технического описания (PDF) - Avago Technologies
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ADJD-S313-QR999 Datasheet PDF : 16 Pages
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Powering the Device
Ground Connection
AGND and DGND must both be set to 0V and
preferably star-connected to a central power source
as shown in the application diagram. A potential
difference between AGND and DGND may cause the
ESD diodes to turn on inadvertently.
Application Diagrams
HOST
SYSTEM
15 SLEEP
DVDD
Pin Information
PIN NAME
1 NC
2 NC
3 NC
4 NC
5 DGND
6 DGND
7 DVDD
8 AGND
9 NC
10 XRST
TYPE
No connect
No connect
No connect
No connect
Ground
Ground
Power
Ground
No connect
Input
11 SCLSLV Input
12 SDASLV Input/Output
(tri-state high)
13 NC
No connect
14 NC
No connect
15 SLEEP Input
16 AGND
17 AGND
18 AGND
19 AVDD
20 NC
12
Ground
Ground
Ground
Power
No connect
XRST
SDA
SCL
HOST
SYSTEM
10 XRST
12 SDASLV
11 SCLSLV
AVDD
19
Voltage
Regulator
AGND
8, 16,
17, 18
DGND DVDD
5, 6
7
Voltage
Regulator
Star-connected ground
DESCRIPTION
No connect. Leave floating.
No connect. Leave floating.
No connect. Leave floating.
No connect. Leave floating.
Tie to digital ground.
Tie to digital ground.
Digital power pin.
Tie to analog ground.
No connect. Leave floating.
Global, asynchronous, active-low system reset. When asserted low, XRST
resets all registers. Minimum reset pulse low is 10 µs and must be provided by
external circuitry.
SDASLV and SCLSLV are the serial interface communications pins. SDASLV is
the bidirectional data pin and SCLSLV is the interface clock. A pull-up resistor
should be tied to SDASLV because it goes tri-state to output logic 1.
No connect. Leave floating.
No connect. Leave floating.
When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog
circuits are powered down and the clock signal is gated away from the core
logic resulting in very low current consumption.
Tie to analog ground.
Tie to analog ground.
Tie to analog ground.
Analog power pin.
No connect. Leave floating.
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