ADIS16265BCCZ(RevF) Просмотр технического описания (PDF) - Analog Devices
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ADIS16265BCCZ Datasheet PDF : 20 Pages
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Data Sheet
ADIS16260/ADIS16265
Global Commands
Data Ready I/O Indicator
The GLOB_CMD register provides trigger bits for several
functions. Setting the assigned bit to 1 starts each operation,
which returns the bit to 0 after completion. For example, set
GLOB_CMD[7] = 1 (DIN = 0xBE80) to execute a software
reset, which stops the sensor operation and runs the device
through its start-up sequence. This sequence includes loading
the control registers with the contents of their respective flash
memory locations prior to producing new data.
Table 18. GLOB_CMD Bit Descriptions
Bits
Description
[15:8]
Not used.
7
Software reset command.
[6:4]
Not used.
3
Flash update command.
2
Auxiliary DAC data latch.
1
Factory calibration restore command.
0
Autonull command.
Power Management
Setting SMPL_PRD[7:0] ≥ 0x08 also sets the sensor to low
power mode. For systems that require lower power dissipation,
in-system characterization helps users to quantify the associated
performance trade-offs. In addition to sensor performance, low
power mode affects SPI data rates (see Table 2). Use SLP_CNT[7:0]
to put the device into sleep mode for a specified period. For
example, SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) puts the
ADIS16260 and ADIS16265 to sleep for 50 seconds.
Table 19. SLP_CNT Bit Descriptions
Bits
Description (Default = 0x0000)
[15:8]
Not used.
[7:0]
Programmable sleep time bits, 0.5 sec/LSB.
INPUT/OUTPUT FUNCTIONS
General-Purpose I/O
DIO1 and DIO2 are configurable, general-purpose I/O lines
that serve multiple purposes according to the following control
register priority: MSC_CTRL, ALM_CTRL, and GPIO_CTRL.
For example, set GPIO_CTRL = 0x0202 (DIN = 0xB302, and
then 0xB202) to configure DIO1 as an input and DIO2 as an
output set high.
Table 20. GPIO_CTRL Bit Descriptions
Bits
Description
[15:10] Not used.
9
General-Purpose I/O Line 2 (DIO2) data level.
8
General-Purpose I/O Line 1 (DIO1) data level.
[7:2]
Not used.
1
General-Purpose I/O Line 2 (DIO2) direction control.
1 = output, 0 = input.
0
General-Purpose I/O Line 1 (DIO1) direction control.
1 = output, 0 = input.
The MSC_CTRL[2:0] bits configure one of the digital I/O lines
as a data ready signal for driving an interrupt. For example, set
MSC_CTRL[2:0] = 100 (DIN = 0xB404) to configure DIO1 as
a negative-pulse data ready signal. The pulse width is between
100 µs and 200 µs over all conditions.
Table 21. MSC_CTRL Bit Descriptions
Bits
Description (Default = 0x0000)
[15:12] Not used.
11
Memory test (cleared upon completion).
1 = enabled, 0 = disabled.
10
Internal self-test enable (cleared upon completion).
1 = enabled, 0 = disabled.
9
Manual self-test, negative stimulus.
1 = enabled, 0 = disabled.
8
Manual self-test, positive stimulus.
1 = enabled, 0 = disabled.
[7:3]
Not used.
2
Data ready enable.
1 = enabled, 0 = disabled.
1
Data ready polarity.
1 = active high, 0 = active low.
0
Data ready line select.
1 = DIO2, 0 = DIO1.
Auxiliary DAC
The 12-bit AUX_DAC line can drive its output to within 5 mV
of the ground reference when it is not sinking current. As the
output approaches 0 V, the linearity begins to degrade (~100 LSB
starting point). As the sink current increases, the nonlinear
range increases. The DAC latch command moves the values of
the AUX_DAC register into the DAC input register, enabling
both bytes to take effect at the same time.
Table 22. AUX_DAC Bit Descriptions
Bits
Description (Default = 0x0000)
[15:12] Not used.
[11:0]
Data bits, scale factor = 0.6105 mV/code.
Offset binary format, 0 V = 0 codes.
Table 23. Setting AUX_DAC = 2 V
DIN
Description
0xB0CC AUX_DAC[7:0] = 0xCC (204 LSB).
0xB10C AUX_DAC[15:8] = 0x0C (3072 LSB).
0xBE04 GLOB_CMD[2] = 1.
Move values into the DAC input register, resulting in
a 2 V output level.
Rev. F | Page 15 of 20
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