ADG791G Просмотр технического описания (PDF) - Analog Devices
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ADG791G Datasheet PDF : 24 Pages
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ADG791A/ADG791G
Parameter1 Conditions
Min
Max
Unit
Description
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition
and after an acknowledge bit.
Fast mode
20 + 0.1 CBB 300
ns
High speed mode
CB = 100 pF max 10
80
ns
CB = 400 pF max 20
160
ns
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
20 + 0.1 CBB 300
ns
High speed mode
CB = 100 pF max 10
40
ns
CB = 400 pF max 20
80
ns
tSP
Fast mode
0
50
ns
Pulse width of suppressed spike
High speed mode 0
10
ns
1 Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD.
2 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
SCL
SDA
t7
PS
t11
t2
t6
t4
t12
t1
t3
t6
t5
t10
S
Figure 2. Timing Diagram for 2-Wire Serial Interface
t8
t9
P
Rev. 0 | Page 8 of 24
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