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ADF7021-V

High Performance, Narrow-Band Transceiver IC

Analog Devices 

ADF7021-V

FREQUENCY SYNTHESIZER

REFERENCE INPUT

The on-board crystal oscillator circuitry (see Figure 32) can use

a quartz crystal as the PLL reference. A quartz crystal with a fre-

quency tolerance of ≤10 ppm for narrow-band applications is

recommended. It is possible to use a quartz crystal with >10 ppm

tolerance, but compensation for the frequency error of the crystal

is necessary to comply with the absolute frequency error speci-

fications of narrow-band regulations (for example, ARIB STD-T67

and ETSI EN 300 220).

The oscillator circuit is enabled by setting Bit DB12 in Register 1

high. It is enabled by default on power-up and is disabled by

bringing CE low. Errors in the crystal can be corrected using

the automatic frequency control (AFC) feature or by adjusting

the fractional-N value (see the N Counter section).

OSC1

OSC2

CP2

CP1

Figure 32. Crystal Oscillator Circuit on the ADF7021-V

Two parallel resonant capacitors are required for oscillation at

the correct frequency. Their values are dependent on the crystal

specification. The resonant capacitors should be selected to

ensure that the series value of capacitance added to the PCB

track capacitance adds up to the specified load capacitance of

the crystal, usually 12 pF to 20 pF. Track capacitance values vary

from 2 pF to 5 pF, depending on board layout. When possible,

choose capacitors that have a very low temperature coefficient

to ensure stable frequency operation over all conditions.

Using a TCXO Reference

A single-ended reference (TCXO, VCXO, or OCXO) can also be

used with the ADF7021-V. This is recommended for applications

that have absolute frequency accuracy requirements of <10 ppm,

such as applications requiring compliance with ARIB STD-T67

or ETSI EN 300 220. The following are two options for inter-

facing the ADF7021-V to an external reference oscillator.

• An oscillator with CMOS output levels can be applied to

OSC2. The internal oscillator circuit should be disabled by

setting Bit DB12 in Register 1 low.

• An oscillator with 0.8 V p-p levels can be ac-coupled through

a 22 pF capacitor into OSC1. The internal oscillator circuit

should be enabled by setting Bit DB12 in Register 1 high.

Programmable Crystal Bias Current

Bias current in the oscillator circuit can be configured from

20 μA to 35 μA by writing to the XTAL_BIAS bits (Register 1,

Bits[DB14:DB13]). Increasing the bias current allows the crystal

oscillator to power up faster.

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the

oscillator section, shown in Figure 32, and supplies a divided-

down, 50:50 mark/space signal to the CLKOUT pin. The

CLKOUT signal is inverted with respect to the reference clock.

An even divide from 2 to 30 is available; this divide number is

set in Register 1, Bits[DB10:DB7]. On power-up, the CLKOUT

defaults to divide-by-8.

VDD

CLKOUT

ENABLE BIT

OSC1

DIVIDER

÷2

1 TO 15

CLKOUT

Figure 33. CLKOUT Stage

To disable CLKOUT, set the divide number to 0. The output

buffer can drive a load of up to 20 pF with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough

to the output. A series resistor (1 kΩ) can be used to slow the

clock edges to reduce these spurs at the CLKOUT frequency.

R Counter

The 3-bit R counter divides the reference input frequency by an

integer from 1 to 7. The divided-down signal is presented as the

reference clock to the phase frequency detector (PFD). The

divide ratio is set in Register 1, Bits[DB6:DB4]. Maximizing the

PFD frequency reduces the N value. This reduces the noise multi-

plied at a rate of 20 log(N) to the output and reduces occurrences

of spurious components.

Register 1 defaults to R = 1 on power-up.

PFD (Hz) = XTAL/R

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 34.

CHARGE

PUMP OUT

VCO

Figure 34. Typical Loop Filter Configuration

The loop should be designed so that the loop bandwidth (LBW) is

approximately 6 kHz. This provides a good compromise between

in-band phase noise and out-of-band spurious rejection. Widening

the LBW excessively reduces the time spent jumping between

frequencies, but it can cause insufficient spurious attenuation.

The loop filter design on the EVAL-ADF7021-VDBxZ should

be used for optimum performance.

Rev. 0 | Page 21 of 60

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