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ADF7010BRU

High Performance ISM Band ASK/FSK/GFSK Transmitter IC

Analog Devices 

ADF7010

CIRCUIT DESCRIPTION

PRESCALER, PHASE FREQUENCY DETECTOR (PFD),

REFERENCE INPUT SECTION

AND CHARGE PUMP

The on-board crystal oscillator circuitry (Figure 2), allows the

The dual-modulus prescaler (P/P + 1) divides the RF signal

use of an inexpensive quartz crystal as the PLL reference. The

oscillator circuit is enabled by setting XOE low. It is enabled

from the VCO to a lower frequency that is manageable by the

CMOS counters.

by default on power-up and is disabled by bringing CE low.

Two parallel resonant capacitors are required for oscillation at

the correct frequency; the value of these is dependent on the

crystal specification. Errors in the crystal can be corrected using

the Error Correction register within the R Register. A single-

The PFD takes inputs from the R Counter and the N Counter

(N = Int + Fraction) and produces an output proportional to the

phase and frequency difference between them. Figure 4 is a

simplified schematic.

ended reference (TCXO, CXO) may be used. The CMOS

levels should be applied to OSC2, with XOE set high.

VP

CHARGE

PUMP

UP

10pF

OSC2

TE 10pF

OSC1 500k⍀

100k⍀

NC

SW1

100k⍀

BUFFER

XTAL OSCILLATOR

DISABLED

TO R COUNTER, AND

CLOCK OUT DIVIDE

Figure 2. Oscillator Circuit on the ADF7010

CLKOUT DIVIDER AND BUFFER

The CLKOUT circuit takes the reference clock signal from the

E oscillator section above and supplies a divided down 50:50

mark-space signal to the CLKOUT pin. An even divide from 2 to 30

is available. This divide is set by the 4 MSBs in the R register.

L On power-up, the CLKOUT defaults to divide by 16.

DVDD

CLKOUT

ENABLE BIT

O OSC1

DIVIDER

1 TO 15

DIVIDE

BY 2

CLKOUT

S Figure 3. CLKOUT Stage

B The output buffer to CLKOUT is enabled by setting Bit DB4 in

the function register high. On power-up, this bit is set high. The

output buffer can drive up to a 20 pF load with a 10% rise time at

O 4.8 MHz. Faster edges can result in some spurious feedthrough

HI

R DIVIDER

D1 Q1

U1

CLR1

U3

CP

HI

N DIVIDER

CLR2

DOWN

D2 Q2

U2

CPGND

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 4. PFD Stage

The PFD includes a delay element that sets the width of the

antibacklash pulse. The typical value for this in the ADF7010 is

3 ns. This pulse ensures that there is no dead zone in the PFD

transfer function and minimizes phase noise and reference spurs.

MUXOUT AND LOCK DETECT

The MUXOUT pin allows the user to access various internal

points in the ADF7010. The state of MUXOUT is controlled by

Bits M1 to M4 in the function register.

to the output. A small series resistor (50 W) can be used to slow

the clock edges to reduce these spurs at FCLK.

REGULATOR READY

This is the default setting on MUXOUT after the transmitter has

R COUNTER

The 4-bit R Counter divides the reference input frequency by an

integer from 1 to 15. The divided down signal is presented as the

reference clock to the phase frequency detector (PFD). The divide

ratio is set in the R register. Maximizing the PFD frequency

reduces the N-value. This reduces the noise multiplied at a rate

of 20 log(N) to the output, as well as reducing occurrences of

spurious components. The R register defaults to R = 1 on power-up.

been powered up. The power-up time of the regulator is typically

50 ms. Since the serial interface is powered from the regulator,

it is necessary for the regulator to be at its nominal voltage

before the ADF7010 can be programmed. The status of the regu-

lator can be monitored at MUXOUT. Once the REGULATOR

READY signal on MUXOUT is high, programming of the

ADF7010 may begin.

REV. 0

–15–

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