ADF4193BCPZ-RL7 Просмотр технического описания (PDF) - Analog Devices

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ADF4193BCPZ-RL7

Low Phase Noise, Fast Settling PLL Frequency Synthesizer

Analog Devices 

ADF4193

Data Sheet

The value of MOD is chosen to give the desired channel step

with the available reference frequency. Thereafter, program the

INT and FRAC words for the desired RF output frequency. See

the Worked Example section for more information.

PFD and Charge Pump

The PFD takes inputs from the R divider and N divider and

produces up and down outputs with a pulse width difference

proportional to the phase difference between the inputs. The

charge pump outputs a net up or down current pulse of a width

equal to this difference, to pump up or pump down the voltage

that is integrated onto the loop filter, which in turn increases or

decreases the VCO output frequency. If the N divider phase lags

the R divider phase, a net up current pulse is produced that

increases the VCO frequency (and thus the phase). If the N

divider phase leads the R divider edge, then a net down pulse is

produced to reduce the VCO frequency and phase. Figure 23 is

a simplified schematic of the PFD and charge pump. The charge

pump is made up of an array of 64 identical cells, each of which

is fully differential. All 64 cells are active during fast lock, but

only one is active during normal operation. Because a single-

ended control voltage is required to tune the VCO, an on-chip,

differential-to-single-ended amplifier is provided for this purpose.

In addition, because the phase-lock loop only controls the

differential voltage generated across the charge pump outputs,

an internal common-mode feedback (CMFB) loop biases the

charge pump outputs at a common-mode voltage of approximately

2 V.

R DIVIDER

D

Q

CLR

CPOUT+

CHARGE

PUMP

ARRAY

[64:1]

CMFB

CLR

D

Q

CPOUT–

N DIVIDER

EN[64:1]

Figure 23. PFD and Differential Charge Pump Simplified Schematic

Differential Charge Pump

The charge pump cell (see Figure 24) has a fully differential

design for best up-to-down current matching. Good matching

is essential to minimize the phase offset created when switching

the charge pump current from its high value (in fast lock mode)

to its nominal value (in normal mode).

To pump up, the up switches are on and PMOS current is

sourced out through CPOUT+; this increases the voltage on the

external loop filter capacitors connected to CPOUT+. Similarly,

the NMOS current sink on CPOUT− decreases the voltage on the

external loop filter capacitors connected to CPOUT−. Therefore,

the differential voltage between CPOUT+ and CPOUT− increases.

To pump down, PMOS current sources out through CPOUT− and

NMOS current sinks in through CPOUT+, which decreases the

(CPOUT+, CPOUT−) differential voltage. The charge pump up/

down matching is improved by an order of magnitude over the

conventional single-ended charge pump that depended on the

matching of two different device types. The up/down matching

in this structure depends on how a PMOS matches a PMOS and

an NMOS matches an NMOS.

VBIAS P

P

P

UP

DOWN

CPOUT+

CPOUT–

DOWN

N

VBIAS N

UP

N

Figure 24. Differential Charge Pump Cell with External Loop Filter Components

Fast Lock Timeout Counters

Timeout counters, clocked at one quarter the PFD reference

frequency, are provided to precisely control the fast locking

operation (see Figure 25). Whenever a new frequency is

programmed, the fast lock timers start and the PLL locks into

wide BW mode with the 64 identical 100 µA charge pump cells

active (6.4 mA total). When the ICP counter times out, the

charge pump current is reduced to 1× by deselecting cells in

binary steps over the next six timer clock cycles, until just one

100 µA cell is active. The charge pump current switching from

6.4 mA to 100 µA equates to an 8-to-1 change in loop bandwidth.

The loop filter must be changed to ensure stability when this

happens. That is the job of the SW1, SW2, and SW3 switches. The

application circuit (shown in Figure 36) shows how they can be

used to reconfigure the loop filter time constants. The application

circuits close to short out external loop filter resistors during fast

lock and open when their counters time out to restore the filter

time constants to their normal values for the 100 µA charge

pump current. Because it takes six timer clock cycles to reduce

the charge pump current to 1×, it is recommended that both

switch timers be programmed to the value of the ICP timer + 7.

WRITE START

TO R0

ICP

TIMEOUT

COUNTER

SW1/SW2

TIMEOUT

COUNTER

SW3

TIMEOUT

COUNTER

FPFD

÷4

CHARGE PUMP

ENABLE LOGIC

EN[64:1]

Figure 25. Fast Lock Timeout Counters

SW3

AOUT

SW1

SW2

SWGND

Rev. F | Page 12 of 32

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