ADF4193(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADF4193 Datasheet PDF : 28 Pages
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ADF4193
MUX REGISTER (R6)
SIGMA-DELTA
AND
LOCK DETECT MODES
RESERVED
MUXOUT
CONTROL
BITS
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M13 M12 M11 M10 0
0
0
0
0
M4 M3 M2 M1 C3 (1) C2 (1) C1 (0)
M13 M12 M11 M10 SIGMA-DELTA MODES
0
0
0
0 INIT STATE, DITHER OFF,
3ns LOCK DETECT THRESHOLD
0
0
1
1 DITHER ON
1
0
0
1 10ns LOCK DETECT THRESHOLD
ALL OTHER STATES
RESERVED
M4 M3 M2 M1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MUXOUT
3-STATE
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
LOGIC HIGH
R COUNTER
RESERVED
SERIAL DATA OUT
LOGIC LOW
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RESERVED
RESERVED
ICP TIMEOUT SIGNAL
SW1/2 TIMEOUT SIGNAL
SW3 TIMEOUT SIGNAL
RESERVED
Figure 35. MUX Register (R6)
With C3, C2, and C1 set to 1, 1, 0, respectively, the MUX
register is programmed.
Σ-Δ and Lock Detect Modes
Bit DB15 to Bit DB12 are used to reconfigure certain PLL
operating modes. In the initialization sequence after power is
applied to the chip, the four bits must first be programmed to
all zeros. This initializes the PLL to a known state with dither
off in the Σ-Δ modulator and a 3 ns PFD error threshold in the
lock detect circuit.
To turn on dither in the Σ-Δ modulator, an additional write
should be made to Register R6 to program bits [DB15:DB12] =
[0011]. However, for lowest noise operation, it is best to leave
dither off.
MUXOUT Modes
These bits control the on-chip multiplexer. See Figure 35 for the
truth table. This pin is useful for diagnosis because it allows the
user to look at various internal points of the chip, such as the
R divider and INT divider outputs.
In addition, it is possible to monitor the programmed timeout
counter intervals on MUXOUT. For example, if the ICP timeout
counter was programmed to 65 (with a 26 MHz PFD), then
following the next write to R0, a pulse width of 10 μs would be
observed on the MUXOUT pin.
Digital lock detect is available via the MUXOUT pin.
To change the lock detect threshold from 3 ns to 10 ns, a
separate write to R6 should be performed to program bits
[DB15:DB12] = [1001]. This should be done for reliable lock
detect operation when the RF frequency is <2 GHz.
A write to R6 that programs bits [DB15:DB12] = [0000] returns
operation to the default state with both dither off and a 3 ns
lock detect threshold.
Reserved Bits
The reserved bits must all be set to 0 for normal operation.
Rev. B | Page 21 of 28
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