ADF4157BCPZ-RL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADF4157BCPZ-RL7 Datasheet PDF : 20 Pages
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ADF4157
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NC
TO R COUNTER
BUFFER
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by
a 2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
2kΩ
2kΩ
AVDD
RFINA
RFINB
Figure 12. RF Input Stage
AGND
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
fRES = fPFD/225
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/225))
(1)
where:
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter (23 to
4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
fPFD = REFIN × [(1 + D)/(R × (1+T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
T is the REFIN divide-by-2 bit (0 or 1).
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
RF N DIVIDER
FROM RF
INPUT STAGE
N-COUNTER
N = INT + FRAC/MOD
TO PFD
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
MOD
REG
FRAC
VALUE
Figure 13. RF N Divider
Rev. 0 | Page 8 of 20
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