ADF4107BRUZ Просмотр технического описания (PDF) - Analog Devices

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ADF4107BRUZ

PLL Frequency Synthesizer

Analog Devices 

ADF4107

Data Sheet

APPLICATIONS

LOCAL OSCILLATOR FOR LMDS BASE STATION

TRANSMITTER

Figure 27 shows the ADF4107 being used with a VCO to

produce the LO for an LMDS base station.

The reference input signal is applied to the circuit at FREFIN

and, in this case, is terminated in 50 Ω. A typical base station

system has either a TCXO or an OCXO driving the reference

input without any 50 Ω termination.

To have a channel spacing of 1 MHz at the output, the 10 MHz

reference input must be divided by 10, using the on-chip

reference divider of the ADF4107.

The charge pump output of the ADF4107 (Pin 2) drives the

loop filter. In calculating the loop filter component values, a

number of items need to be considered. In this example, the

loop filter was designed so that the overall phase margin for the

system would be 45°.

Other PLL system specifications are:

KD = 5.0 mA

KV = 80 MHz/V

Loop bandwidth = 70 kHz

FPFD = 1 MHz

N = 6300

Extra reference spur attenuation = 10 dB

All of these specifications are needed and used to derive the

loop filter component values shown in Figure 27.

Figure 27 gives a typical phase noise performance of −83 dBc/Hz

at 1 kHz offset from the carrier. Spurs are better than −70 dBc.

The loop filter output drives the VCO, which, in turn, is fed

back to the RF input of the PLL synthesizer, and drives the RF

output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the RFIN

terminal of the synthesizer.

In a PLL system, it is important to know when the system is in

lock. In Figure 27, this is accomplished by using the MUXOUT

signal from the synthesizer. The MUXOUT pin can be

programmed to monitor various internal signals in the

synthesizer. One of these is the LD or lock detect signal.

VDD

VP

RFOUT

FREFIN

1000pF

51Ω

1000pF

7

15

16

AVDD DVDD VP

CP 2

8 REFIN

100pF

1.7kΩ

7.5kΩ

14

2 VCC

100pF

18Ω

100pF 18Ω

10

47pF V956ME01

18Ω

5.1kΩ

ADF4107

820pF

CE

CLK

DATA

MUXOUT 14

LOCK

DETECT

LE

100pF

1 RSET

RFINA 6

RFINB 5

51Ω

1, 3, 4, 5, 7, 8,

9, 11, 12, 13

34 9

100pF

NOTES:

1. DECOUPLING CAPACITORS (0.1µF/10pF) ON AVDD, DVDD, AND

VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 27. 6.3 GHz Local Oscillator Using the ADF4107

Rev. D | Page 18 of 20

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