ADF41020BCPZ-RL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADF41020BCPZ-RL7 Datasheet PDF : 16 Pages
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ADF41020
CP Three-State
Bit DB8 (F3) controls the CP output pin. With the bit set high,
the CP output is put into three-state. With the bit set low, the
CP output is enabled.
Device Programming After Initial Power-Up
After initial power up of the device, there are three methods for
programming the device: function latch, CE pin, and counter
reset.
Function Latch Method
1. Apply VDD.
2. Program the function latch load (10 in two LSBs of the
control word), making sure that the F1 bit is programmed
to a 0.
3. Do an R load (00 in two LSBs).
4. Do an N (A, B) load (01 in two LSBs).
CE Pin Method
1. Apply VDD.
2. Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
3. Program the function latch (10).
4. Program the R counter latch (00).
5. Program the N (A, B) counter latch (01).
Data Sheet
6. Bring CE high to take the device out of power-down. The
R and N (A, B) counters now resume counting in close
alignment.
Note that after CE goes high, a 1 µs duration may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check
for channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled
as long as it is programmed at least once after VDD is initially
applied.
Counter Reset Method
1. Apply VDD.
2. Do a function latch load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
3. Do an R counter load (00 in two LSBs).
4. Do an N (A, B) counter load (01 in two LSBs).
5. Do a function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides direct control over the internal
counter reset.
Rev. 0 | Page 14 of 16
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